Memory device and manufacturing method thereof

A memory device, comprising:

• a substrate;
• a plurality of conductive layers and a plurality of dielectric layers interlaced and stacked on the substrate;
• a memory structure penetrating through the conductive layers and the dielectric layers, wherein the memory structure includes a channel structure and a conductive plug disposed on the channel structure;
• a select gate structure disposed on a sidewall of the memory structure, wherein the select gate structure includes a select gate dielectric layer and a select gate electrode surrounded by the select gate dielectric layer, wherein a top surface of the select gate electrode is between a top surface of the conductive plug and a top surface of a topmost layer of the conductive layers, wherein the select gate structure further comprises a cap layer on the select gate electrode;
• and
• a bit line contact electrically connected to the memory structure, wherein the bit line contact penetrates through the cap layer and the select gate dielectric layer of the select gate structure.