US 12,598,701 B2Granted

Semiconductor device with selection structure and method for fabricating the same

AssigneeNanya Technology Corporation

InventorHsih-Yang Chiu

Life of this patent

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Abstract

A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Claims14

Dependent claims

A semiconductor device, comprising:

a first top selection structure positioned at a same vertical level as a main signal pad, along a first direction, and separated from the main signal pad;
a fourth top selection structure positioned at the same vertical level as the main signal pad and separated from the first top selection structure along the first direction with the main signal pad interposed therebetween;
a first ground layer positioned at the same vertical level as the main signal pad and separated from the main signal pad and the first top selection structure;
a second ground layer positioned at the same vertical level as the main signal pad and separated from the fourth top selection structure and the main signal pad;
a first bottom selection structure positioned at a vertical level lower than the main signal pad and partially overlapped with the first top selection structure and the first ground layer in a top-view perspective;
a second bottom selection structure positioned at the same vertical level as the first bottom selection structure and partially overlapped with the fourth top selection structure and the second ground layer in a top-view perspective;
a first top via positioned between the first ground layer and the first bottom selection structure;
a third top via positioned between the second ground layer and the second bottom selection structure;
a second top via positioned between the first top selection structure and the first bottom selection structure;
a fourth top via positioned between the fourth top selection structure and the second bottom selection structure;
and
a first insulating layer positioned between the second top via and the first bottom selection structure;
a second insulating layer positioned between the fourth top via and the second bottom selection structure.

10 more elements

A method for fabricating a semiconductor device, comprising:

forming a first bottom selection structure over a substrate and comprising a first connecting bottom selection layer, a first vertical bottom selection layer extending from the first connecting bottom selection layer along a first direction, and a first horizontal bottom selection layer extending from the first connecting bottom selection layer along a second direction different from the first direction;
forming a plurality of second top vias on the first horizontal bottom selection layer and the first vertical bottom selection layer and forming a first top via on the first connecting bottom selection layer;
forming a plurality of first insulating layers between the plurality of second top vias and the first horizontal bottom selection layer and between the plurality of second top vias and the first vertical bottom selection layer;
forming a first ground layer on the first top via;
forming a first top selection structure and a second top selection structure on the plurality of second top vias, respectively and correspondingly;
forming a main signal pad at a same vertical level as the first ground layer and separated from the first top selection structure and the second top selection structure;
and
forming a wiring pad on the main signal pad, the first top selection structure, and the second top selection structure;
wherein the first top selection structure is partially overlapped with the first horizontal bottom selection layer and the second top selection structure is partially overlapped with the first vertical bottom selection layer in a top-view perspective.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/382,207Filed 20 Oct 2023 · division
Priority: 14 Jun 2023
Published: US 2024/0422905 A119 Dec 2024
Granted: 7 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H05K 1/112
Pads for surface mounting, e.g. lay-out: directly combined with via connections
H10W 70/685
Shapes or dispositions thereof: comprising multiple insulating layers
H05K
Printed circuits
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

Application18/209,755Parent of this division · filed 14 Jun 2023
US 2024/0422906 A1Pre-grant publication · published 19 Dec 2024
US 12,453,008 B2Parent of this division
US 2024/0422905 A1Published application
US 12,598,701 B2This patent

From the US filing history. Foreign family members aren’t listed.