Low-leakage ESD protection circuit and operating method thereof

A semiconductor device, comprising:

• a detection circuit configured to generate a first signal in response to an Electrostatic discharge (ESD) event;
• a discharge circuit comprising a P-type transistor having a gate electrode electrically connected to the detection circuit and configured to receive the first signal, a first electrode electrically coupled to a first node, a second electrode electrically coupled to a second node, and a bulk electrode electrically coupled to the first node;
• and
• a biasing circuit electrically connected to the discharge circuit, wherein:
• the P-type transistor has a first width larger than a second width of any transistor or diode in the detection circuit and the biasing circuit;
• the first signal triggers a current associated with the ESD event to flow through the discharge circuit and the biasing circuit;
• the first electrode and the second electrode of the P-type transistor are a first P-type doped region and a second P-type doped region formed within a first N-type well region above a P-type substrate, respectively;
• a first portion and a second portion of the bulk electrode are a first N-type doped region and a second N-type doped region within the first N-type well region, the first N-type doped region and the second N-type doped region are electrically connected to the first node, the first portion and the first electrode are separated by a first isolation component, and the second portion and the second electrode are separated by a second isolation component;
• the first P-type doped region and the second P-type doped region are disposed between the first N-type doped region and the second N-type doped region within the first N-type well region;
• the biasing circuit comprises a diode including an anode and a cathode that are formed within a second N-type well region above the P-type substrate, the anode is a third P-type doped region electrically coupled to the third node, the cathode is a third N-type doped region electrically coupled to the second node, the third P-type doped region and the third N-type doped region are separated by a third isolation component, and the first N-type well region and the second N-type well region are separated by a fourth isolation component;
• the first N-type doped region is disposed between the first P-type doped region and the third P-type doped region;
• the third P-type doped region is disposed between the third N-type doped region and the first N-type doped region;
• a diode-free conductive element is electrically connected between the first P-type doped region and the third P-type doped region;
• in response to the ESD event occurring at the first node, a first discharge current path is established between the first electrode of the P-type transistor and the third P-type doped region;
• and
• in response to the ESD event, a second discharge path is established from the second P-type doped region to the third N-type doped region through the first N-type well region, the P-type substrate, and the second N-type well region.

A semiconductor device, comprising:

• a detection circuit electrically coupled between a first node and a second node;
• a discharge circuit electrically coupled between the first node and a third node;
• and
• a biasing circuit electrically coupled between the second node and the third node, wherein:
• the detection circuit is configured to turn on the discharge circuit in response to an Electrostatic discharge (ESD) event occurring at the first node and keep the discharge circuit off when no ESD event occurs;
• the discharge circuit comprises a P-type transistor having a gate electrode electrically coupled to the fourth node, a first electrode electrically coupled to the third node, a second electrode electrically coupled to the first node, and a bulk electrode electrically coupled to the first node;
• a first width of the P-type transistor is larger than a second width of any transistor or diode in the detection circuit and the biasing circuit;
• the first electrode and the second electrode of the P-type transistor are a first P-type doped region and a second P-type doped region formed within a first N-type well region above a P-type substrate, respectively;
• a first portion and a second portion of the bulk electrode are a first N-type doped region and a second N-type doped region within the first N-type well region, the first N-type doped region and the second N-type doped region are electrically connected to the first node, the first portion and the first electrode are separated by a first isolation component, and the second portion and the second electrode are separated by a second isolation component;
• the first P-type doped region and the second P-type doped region are disposed between the first N-type doped region and the second N-type doped region within the first N-type well region;
• the biasing circuit comprises a diode including an anode and a cathode that are formed within a second N-type well region above the P-type substrate, the anode is a third P-type doped region electrically coupled to the third node, the cathode is a third N-type doped region electrically coupled to the second node, the third P-type doped region and the third N-type doped region are separated by a third isolation component, and the first N-type well region and the second N-type well region are separated by a fourth isolation component;
• the first N-type doped region is disposed between the first P-type doped region and the third P-type doped region;
• the third P-type doped region is disposed between the third N-type doped region and the first N-type doped region;
• a diode-free conductive element is electrically connected between the first P-type doped region and the third P-type doped region;
• in response to the ESD event occurring at the first node, a first discharge current path is established between the first electrode of the P-type transistor and the third P-type doped region;
• and
• in response to the ESD event, a second discharge path is established from the second P-type doped region to the third N-type doped region through the first N-type well region, the P-type substrate, and the second N-type well region.