Multi-stack ferroelectric memory structure

A memory device comprising:

• a first memory cell and a second memory cell,
• wherein the first memory cell comprises a first gate layer portion,
• wherein the first gate layer portion comprises a first gate electrode layer and one or more first electrically insulating layers,
• wherein the second memory cell comprises a second gate layer portion,
• wherein the second gate layer portion comprises a second gate electrode layer and one or more second electrically insulating layers;
• and
• a channel structure extending through the first gate layer portion and the second gate layer portion,
• wherein the channel structure comprises a first channel portion associated with the first memory cell and further comprises a second channel portion associated with the second memory cell,
• wherein the first memory cell further comprises a first spontaneously-polarizable portion and a first floating gate, wherein the first spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion,
• wherein the second memory cell further comprises a second spontaneously-polarizable portion and a second floating gate, wherein the second spontaneously-polarizable portion and the second floating gate are disposed between the second gate layer portion and the second channel portion,
• wherein the first gate layer portion, the first floating gate, and the first channel portion form a first field-effect transistor structure,
• wherein the second gate layer portion, the second floating gate, and the second channel portion form a second field-effect transistor structure,
• wherein a height of the first spontaneously-polarizable portion is less than a height of the first floating gate when measured along an axis parallel to a longitudinal axis of the channel structure, and
• wherein a height of the second spontaneously-polarizable portion is less than a height of the second floating gate when measured along the axis parallel to the longitudinal axis of the channel structure.

A memory device comprising:

• a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks comprises a gate electrode layer and one or more electrically insulating layers;
• and
• one or more channel structures extending through the plurality of gate layer stacks,
• wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells of the memory device,
• wherein a first field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises:
• a first gate layer portion of a first gate layer stack of the plurality of gate layer stacks;
• a first channel portion of a channel structure of the one or more channel structures;
• a spontaneously-polarizable portion;
• and
• a first floating gate,
• wherein the spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion, and
• wherein the spontaneously-polarizable portion is U-shaped around the first floating gate of the first field-effect transistor based memory cell.