On-chip peltier cooling device and manufacturing method thereof

An on-chip peltier cooling device, comprising:

• a first type well and a second type well located adjacent to each other in a semiconductor substrate;
• a first polysilicon gate and first dummy gates located on the first type well, and a second polysilicon gate and second dummy gates located on the second type well, wherein the first dummy gate and the second dummy gate are respectively formed as a two-segment structure with an interval, wherein there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate, and the second segment of the first dummy gate is connected to the second segment of the second dummy gate;
• first type doped regions located in the semiconductor substrate, the first type doped regions at least overlap with orthographic projection regions of first segments of the first dummy gates on the semiconductor substrate and orthographic projection regions of the second polysilicon gate and the second segments of the second dummy gates on the semiconductor substrate, and the first segment of the first dummy gate is doped as the first type;
• second type doped regions located in the semiconductor substrate, the second type doped regions at least overlap with orthographic projection regions of first segments of the second dummy gates on the semiconductor substrate and orthographic projection regions of the first polysilicon gate and the second segments of the first dummy gates on the semiconductor substrate, and the second segment of the second dummy gate is doped as the second type;
• and
• a first via located on the first segment of the first dummy gate and a second via located on the first segment of the second dummy gate.

A method for manufacturing an on-chip peltier cooling device, comprising:

• forming a gate oxide layer on a first type well in a semiconductor substrate, wherein the gate oxide layer exposes a portion of the first type well;
• forming a polysilicon gate and dummy gates on the first type well, and the dummy gate is formed as a two-segment structure with an interval, wherein there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate, and the interval is located on the portion of the first type well which is exposed;
• forming first type doped regions in the first type well, the first type doped region at least overlaps with an orthographic projection region of a first segment of the dummy gate on the semiconductor substrate, and the first segment of the dummy gate is doped as the first type;
• forming a second type doped region in the first type of well, and the second type doped region at least overlaps with orthographic projection regions of the polysilicon gate and second segments of the dummy gates on the semiconductor substrate, and the second segment of the dummy gate is doped as the second type;
• and
• forming a first via on the first segment and a second via on the second segment, respectively.