US 12,119,335 B2 · Interconnection structures for high bandwidth data transfer

Abstract

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Claims21

Dependent claims

A semiconductor memory module comprising:

a module substrate comprising active components and passive components, wherein the active components comprise companion physical layers, a memory controller, a SERDES, and an I/O connection,
wherein the SERDES and the I/O connection are communicatively coupled with a serial communication link, and
wherein the I/O connection is located a communication distance greater than 8 mm from the companion physical layers;
a high bandwidth semiconductor chip comprising a physical layer physically secured to the module substrate, wherein the physical layer of the high bandwidth semiconductor chip is communicatively coupled to the SERDES via a companion parallel connection, the companion physical layers, a parallel communication link, and the memory controller.

1 more element

Dependencies are inferred from the claim text.

Interconnection structures for high bandwidth data transfer

Life of this patent

Interconnection structures for high bandwidth data transfer

Life of this patent

Abstract

Claims21