Method of manufacturing capacitor connecting line of memory

A method of manufacturing a capacitor connecting line of a memory, comprising:

• forming a bit line layer and a first dielectric layer on a substrate sequentially;
• patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures on tops of the bit line structures, wherein a width of a top cross section of the dielectric structures is larger than a width of a cross section of the bit line structures;
• forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, to completely cover the bit line structures and the dielectric structures;
• patterning the insulating layer with the dielectric structures as a mask in the first direction, forming first isolation structures on sidewalls of the bit line structures, and patterning the insulating layer in a second direction, to form second isolation structures arranged at intervals between adjacent bit line structures;
• and
• forming conductive structures between the first isolation structures and the second isolation structures, and forming storage node contact structures.