One-time programmable memory device including anti-fuse element
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
Life of this patent
Estimating the term…
Abstract
A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.
Claims20
A memory device comprising:
- a transistor over a substrate;
- an anti-fuse element over the substrate and connected to the transistor in series;
- a source/drain contact connected to a source/drain region of the transistor;
- a first gate via connected to a first gate structure of the transistor, wherein the first gate structure of the transistor extends along a first direction in a top view;
- and
- a second gate via connected to a second gate structure of the anti-fuse element, wherein the second gate via is between the first gate via and the source/drain contact along the first direction in the top view.
A memory device comprising:
- an anti-fuse element over a substrate and comprising:
- a first fin structure over the substrate;
- and
- a first gate structure across the first fin structure and extending in a first direction in a top view;
- a transistor over the substrate and comprising:
- the first fin structure;
- a second gate structure across the first fin structure;
- and
- a first source/drain region and a second source/drain region on the first fin structure and on opposite sides of the second gate structure, wherein the first source/drain region is between the first gate structure and the second gate structure;
- a source/drain contact connected to the second source/drain region;
- a first gate via connected to the first gate structure;
- and
- a second gate via connected to the second gate structure, wherein a lateral distance between the first gate via and the source/drain contact along the first direction is less than a lateral distance between the second gate via and the source/drain contact along the first direction in the top view.
A memory device comprising:
- a transistor over a substrate and comprising:
- a semiconductor fin over the substrate and extending in a first direction in a top view;
- a first gate structure over the substrate and covering the semiconductor fin;
- and
- a first source/drain region and a second source/drain region on the semiconductor fin and on opposite sides of the first gate structure;
- an anti-fuse element over the substrate, wherein the transistor and the anti-fuse element are arranged in the first direction in the top view, and the anti-fuse element comprises:
- the semiconductor fin;
- and
- a second gate structure across the semiconductor fin and adjacent to the first source/drain region;
- a first gate via connected to the first gate structure;
- and
- a second gate via connected to the second gate structure, wherein a minimum distance between the first gate via and the semiconductor fin is greater than a minimum distance between the second gate via and the semiconductor fin in a cross-sectional view.
Dependencies are inferred from the claim text.