US 11,910,615 B2 · Memory device and manufacturing method thereof

Abstract

A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

Claims20

Dependent claims

A memory device, comprising:

a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a pair of dielectric blocks respectively disposed alongside the first conductive line and the second conductive line;
a memory layer, disposed between the pair of dielectric blocks and penetrating through the first conductive layers and the first dielectric layers;
and
a channel material layer, disposed between the pair of dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein each of the pair of dielectric blocks has an extended portion located between the memory layer and one of the first conductive layers, and a material of the pair of dielectric blocks has a dielectric constant lower than that of a material of the memory layer.

5 more elements

A memory device, comprising:

a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a first dielectric block and a second dielectric block respectively disposed alongside the first conductive line and the second conductive line;
a memory layer, disposed between and extending between the first and second dielectric blocks, and penetrating through the first conductive layers and the first dielectric layers;
and
a channel material layer, disposed between and extending between the first and second dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein the first dielectric block has a first extended portion located between the memory layer and one of the first conductive layers, the second dielectric block has a second extended portion between the memory layer and the one of the first conductive layers.

5 more elements

A memory device, comprising:

a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a first dielectric block and a second dielectric block respectively disposed alongside the first conductive line and the second conductive line, wherein the first dielectric block and the second dielectric block are of a same material including a low-k dielectric material;
a memory layer, disposed between and extending between the first and second dielectric blocks, and penetrating through the first conductive layers and the first dielectric layers;
and
a channel material layer, disposed between and extending between the first and second dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein the first dielectric block has a first extended portion located between the memory layer and one of the first conductive layers, the second dielectric block has a second extended portion between the memory layer and the one of the first conductive layers.

5 more elements

Dependencies are inferred from the claim text.

Memory device and manufacturing method thereof

Life of this patent

Memory device and manufacturing method thereof

Life of this patent

Abstract

Claims20