Microelectronic devices with source region vertically between tiered decks, and related methods and systems

A method of forming a microelectronic device, the method comprising:

• forming a lower stack structure comprising a vertically alternating sequence of insulative structures and sacrificial structures arranged in tiers;
• forming a lower array of pillar openings extending through the lower stack structure;
• forming, above the lower stack structure and in at least upper portions of the pillar openings of the lower array, at least one sacrificial material;
• forming, above the at least one sacrificial material, an upper stack structure comprising an additional vertically alternating sequence of additional insulative structures and additional sacrificial structures arranged in additional tiers;
• forming an upper array of pillar openings extending through the upper stack structure;
• removing the at least one sacrificial material to form extended openings, the extended openings comprising:
• the pillar openings of the upper array,
• the pillar openings of the lower array, and
• a cavity formed by removing the at least one sacrificial material;
• conformally forming cell material in the extended openings;
• removing the cell material from the cavity, leaving the cell material in the pillar openings of the upper array to form an upper array of pillars, and leaving the cell material in the pillar openings of the lower array to form a lower array of pillars;
• and
• forming at least one conductive material in the cavity to form an interdeck source region vertically interposed between the upper array of pillars and the lower array of pillars;
• and
• replacing the sacrificial structures of the lower stack structure and of the upper stack structure with conductive structures,
• the method forming a microelectronic device comprising:
• a pair of stack structures, the pair comprising:
• the lower stack structure;
• and
• the upper stack structure overlying the lower stack structure,
• the lower stack structure and the upper stack structure each comprising a respective group of the vertically alternating sequence of the insulative structures and the conductive structures arranged in the tiers;
• the interdeck source region vertically interposed between the lower stack structure and the upper stack structure, the interdeck source region comprising at least one conductive material comprising, along a lower surface thereof, an array of V-shaped extensions;
• the upper array of pillars extending, through the upper stack structure, from proximate the interdeck source region toward a first drain region above the upper stack structure;
• and
• the lower array of pillars extending, through the lower stack structure, from proximate the interdeck source region toward a second drain region below the lower stack structure.

A microelectronic device, comprising:

• at least two blocks, each of the blocks comprising:
• a source region vertically interposed between a lower stack structure and an upper stack structure, the lower stack structure and the upper stack structure each comprising insulative structures vertically alternating with conductive structures, the source region comprising at least one conductive material comprising, along a lower surface thereof, an array of V-shaped extensions;
• a lower pillar array extending through the lower stack structure;
• an upper pillar array extending through the upper stack structure;
• a lower drain region below the lower pillar array;
• and
• an upper drain region above the upper pillar array;
• a slit structure horizontally interposed between neighboring blocks of the at least two blocks;
• and
• conductive bridge structures spanning the slit structure, from the source region of one of the neighboring blocks to the source region of another of the neighboring blocks.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and to the output device;
• and
• a memory device operably coupled to the processor device and comprising at least one microelectronic device structure, the at least one microelectronic device structure comprising:
• a source region vertically interposed between a pair of stack structures, each of the stack structures comprising insulative structures vertically interleaved with conductive structures;
• an array of support structures extending through the source region, the support structures comprising an insulative material;
• and
• pillars extending through one stack structure of the pair of stack structures, the pillars comprising a channel material extending from the source region either to an upper drain region above the pair of stack structures or to a lower drain region below the pair of stack structures.