Vertical memory device with tri-layer channel

A vertical memory device, comprising:

• a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate;
• a channel structure extending in the first direction from the substrate to penetrate the gate stack structure;
• and
• charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure,
• wherein the channel structure comprises an insulating pillar formed at a center thereof and channel layers formed to surround the insulating pillar,
• wherein each of the channel layers comprises an undoped channel area, an n-type doped buried channel area formed to surround the undoped channel area, and a p-type doped barrier area formed to surround the n-type doped buried channel area.