Semiconductor structure, integrated circuit device, and method of forming semiconductor structure

#The topography of a semiconductor structure is getting increasingly crucial in the manufacture of a multi-level integrated circuit device. The topography variation can result from different number of deposition layers in different regions of the semiconductor structure, in which an area with higher topography is more susceptible to the etching in a photolithographic process than a lower topography area.

#Typically, a protection film is applied over the entire higher topographic area to prevent such area from damage of the etching. Nonetheless, the desired property of optical materials utilized, e.g., an anti-reflective coating to attenuate or absorb light reflected from the substrate surface into a subsequent photoresist, in the lithographic process is usually affected by the protection film.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIG. 1 is a representative top down view of an implementation of a semiconductor structure, in accordance with some embodiments.

#FIG. 2A-2B is the representative cross sectional side views of some embodiment illustrating an integrated circuit device in the process of forming a semiconductor structure.

#The following disclosure provides various embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

#The singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Therefore, reference to, for example, a topography region includes aspects having two or more such topography regions, unless the context clearly indicates otherwise. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

#Although the present disclosure is explained by references of the formation of a semiconductor structure in an integrated circuit device, it will be appreciated that it is equally applicable to any lithographic manufacturing process where the semiconductor structure can be advantageously formed on a surface of a substrate.