Semiconductor memory devices

A semiconductor memory device comprising:

• a first semiconductor layer and a second semiconductor layer on the first semiconductor layer;
• a plurality of gate electrodes on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer;
• and
• a plurality of channel structures penetrating the first and second semiconductor layers and the plurality of gate electrodes in the first direction, each of the plurality of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the channel layer being connected to the first semiconductor layer, and the gate insulating film including an upper charge storage film in contact with a side surface of the second semiconductor layer.

A semiconductor memory device comprising:

• a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer;
• a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, the plurality of gate electrodes forming a word line cut in the first direction that separates the plurality of gate electrodes in a second direction perpendicular to the first direction;
• and
• a plurality of channel structures penetrating the second and third semiconductor layers and the plurality of the gate electrodes in the first direction, each respective channel structure of the plurality of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the third semiconductor layer including an opening that partially exposes an upper surface of the first semiconductor layer, the second semiconductor layer includes a support connection structure in contact with the first semiconductor layer at the opening, the gate insulating film including an upper tunnel insulating film, an upper charge blocking film, and an upper charge storage film between the upper tunnel insulating film and the upper charge blocking film, and the upper charge storage film including an upper cover protruding in the second direction toward the outside of the respective channel structure.