US 10,872,858 B2Granted

Semiconductor memory device

AssigneesUnited Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.

InventorsHong-Ru Liu, Kuei-Hsuan Yu

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Abstract

A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, and a plurality of bit lines. The semiconductor substrate includes a plurality of active areas. The word lines are disposed parallel to one another, and each of the word lines is elongated in a first direction. Each of the word lines overlaps at least one of the active areas. The bit lines are disposed parallel to one another, and each of the bit lines is elongated in a second direction. Each of the bit lines overlaps at least one of the active areas. The bit lines cross the word lines. An included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees.

Claims9

Dependent claims

A semiconductor memory device, comprising:

a semiconductor substrate comprising active areas;
word lines disposed parallel to one another, and each of the word lines being elongated in a first direction, wherein each of the word lines overlaps at least one of the active areas;
and
bit lines disposed parallel to one another, and each of the bit lines being elongated in a second direction, wherein each of the bit lines overlaps at least one of the active areas, the bit lines cross the word lines, and an included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees, wherein each of the active areas is elongated in a third direction, and the third direction is not perpendicular to the first direction and the second direction, wherein an included angle between the third direction and the first direction is smaller than 90 degrees and is larger than the included angle between the first direction and the second direction.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 16/027,283Filed 4 Jul 2018
Priority: CN 2017 1 076159230 Aug 2017
Published: US 2019/0067183 A128 Feb 2019
Granted: 22 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

US 2019/0067183 A1Pre-grant publication · published 28 Feb 2019
US 10,872,858 B2This patent

From the US filing history. Foreign family members aren’t listed.

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