Method for manufacturing embedded non-volatile memory

A method for manufacturing a semiconductor device, the method comprising:

• forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
• forming a high voltage well in the third region;
• forming a first device structure and a second device structure separated from the first device structure on the first region, forming each of the first device structure and the second device structure further comprising:
• forming a trap storage structure comprising a first oxide layer, a first nitride layer and a second oxide layer stacked on the substrate in sequence;
• forming a control gate directly on the trap storage structure;
• forming a cap structure on the control gate to form a stacked structure;
• and
• forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure, wherein a bottom surface of each of the spacers and a bottom surface of the control gate are formed to entirely contact a same top surface of the second oxide layer;
• forming a first word line well, a well, and a second word line well in the first region, wherein the first word line well and the second word line well are respectively adjacent to the first device structure and the second device structure, and the well is located between the first device structure and the second device structure and is opposite to the first word line well and the second word line well respectively;
• forming a first gap oxide layer and a second gap oxide layer respectively on a sidewall of one of the spacers of the first device structure and a sidewall of one of the spacers of the second device structure, wherein forming the first gap oxide layer is performed such that the first gap oxide layer is between the first and second device structures and in contact with a sidewall of the trap storage structure;
• removing the first gap oxide layer;
• forming a source line in the well;
• forming a logic well in the second region;
• and
• forming a first word line on the first word line well adjacent to the first gap oxide layer, a second word line on the second word line well adjacent to the second gap oxide layer, a gate of a high voltage device on the high voltage well, and a gate of a logic device on the logic well.

A method for manufacturing a semiconductor device, the method comprising:

• forming a first device structure on a substrate, forming the first device structure further comprising:
• forming a first trap storage structure comprising a first oxide layer, a first nitride layer and a second oxide layer stacked on the substrate in sequence;
• forming a first control gate directly on the first trap storage structure;
• forming a first cap structure on the first control gate to form a first stacked structure;
• and
• forming a plurality of first spacers respectively on a plurality of sidewalls of the first stacked structure, wherein a bottom surface of each of the first spacers is formed to entirely contact the second oxide layer;
• forming a first word line well and a source line in the substrate at opposite sides of the first stacked structure respectively;
• forming a first gate oxide layer simultaneously on the first word line well and a sidewall of one of the first spacers;
• forming a first word line on the first gate oxide layer on the first word line well and the sidewall of the one of the first spacers;
• and
• forming a second gate oxide layer in contact with the source line, the first oxide layer, the first nitride layer, and the second oxide layer.