Semiconductor arrangement with capacitor and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
Life of this patent
Estimating the term…
Abstract
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
Claims20
A method of forming a semiconductor arrangement comprising:
- forming a bit line in a first, single, dielectric layer over an active region of the semiconductor arrangement and a first metal structure in the first, single, dielectric layer;
- forming a second dielectric layer over the first, single, dielectric layer, wherein a second metal structure is embedded in the second dielectric layer;
- forming a first opening by removing the second metal structure, wherein the first metal structure is exposed through the first opening;
- forming a first electrode, of a capacitor, in the first opening to overlie the first metal structure;
- forming an insulating layer, of the capacitor, in the first opening over the first electrode;
- and
- forming a second electrode, of the capacitor, in the first opening over the insulating layer.
A method of forming a semiconductor arrangement comprising:
- forming a first dielectric layer, wherein a first metal structure is embedded in the first dielectric layer;
- forming a first opening by removing the first metal structure;
- forming a first electrode, of a capacitor, in the first opening;
- forming an insulating layer, of the capacitor, in the first opening over the first electrode;
- forming a second electrode, of the capacitor, in the first opening over the insulating layer;
- etching the second electrode and the insulating layer to expose a sidewall of the insulating layer;
- and
- forming an etch stop layer over the second electrode, wherein the etch stop layer directly contacts the sidewall of the insulating layer.
A method of forming a semiconductor arrangement comprising:
- forming a stacked arrangement of metal structures in a set of dielectric layers;
- removing the metal structures to define an opening extending through the set of dielectric layers;
- forming a first electrode, of a capacitor, in the opening;
- forming an insulating layer, of the capacitor, in the opening over the first electrode;
- forming a second electrode, of the capacitor, in opening over the insulating layer;
- and
- forming a layer over the opening to cap the opening, wherein an empty space is defined between the layer and the second electrode.
Dependencies are inferred from the claim text.