Array substrate, manufacturing method thereof and display device

A method of manufacturing an array substrate, comprising:

• forming a gate electrode layer, an active layer and a source-drain electrode layer on a substrate,
• wherein the substrate comprises a storage capacitance region thereon, in the storage capacitance region, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped,
• wherein the method further comprises
• forming a gate insulation layer between the gate electrode layer and the active layer, and
• forming an etch-stopper layer between the active layer and the source-drain electrode layer,
• wherein the etch-stopper layer is an insulating layer, and
• wherein, in the storage capacitance region, the gate electrode layer and the active layer are spatially separated by the gate insulation layer so as to form a capacitor between them, and the active layer and the source-drain electrode layer are spatially separated by the etch-stopper layer so as to form another capacitor between them,
• wherein, upon the gate electrode layer being formed, a portion in the storage capacitance region is formed;
• upon the gate insulation layer being formed, a portion in the storage capacitance region is formed;
• upon the active layer being formed, a portion in the storage capacitance region is formed;
• upon the etch-stopper layer being formed, a portion in the storage capacitance region is formed;
• and upon the source-drain electrode layer being formed, a portion in the storage capacitance region is formed,
• wherein the method further comprises etching the gate insulation layer in the storage capacitance region to be thinned, after the gate insulation layer is formed, and
• wherein the method further comprises etching the gate insulation layer at a contact hole predetermined to be formed in the gate insulation layer to be thinned, while etching the gate insulation layer in the storage capacitance region to be thinned.