Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
AssigneeGlobalWafers Co., Ltd.
InventorAlex Usenko
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AssigneeGlobalWafers Co., Ltd.
InventorAlex Usenko
Estimating the term…
A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
A method of preparing a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the semiconductor handle substrate and the other of which is a back surface of the semiconductor handle substrate, an imaginary central plane between the front surface and the back surface, a circumferential edge joining the front and back surfaces of the semiconductor handle substrate, a front surface region extending from the front surface and toward the central plane and having a depth, FSD, and a bulk region between the front and back surfaces of the semiconductor handle substrate, wherein the semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm, and the method comprises:
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