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US 10,373,948 B2Granted
On-die system electrostatic discharge protection
AssigneeIntel Corporation
InventorsChristopher P. Mozak, Victor Zia, Gabriel J. Thompson
Life of this patent
Estimating the term…
Abstract
Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node.
Claims19
An apparatus comprising:
- a first transistor coupled between a node and a supply node, the first transistor including a gate;
- a second transistor coupled between the node and a ground node, the second transistor including a gate coupled to the gate of the first transistor;
- an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node;
- a transistor coupled between the additional node and the supply node;
- a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node;
- and
- a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor.
4 more elements
An apparatus comprising:
- an input/output (I/O) node, a supply node, and a ground node;
- a driver circuit including a first transistor coupled between the I/O node and the supply node, and a second transistor coupled between the I/O node and the ground node, the first transistor including a gate coupled to a gate of the second transistor;
- an electrostatic discharge (ESD) protection unit including a first diode coupled between the I/O node and the ground node, a second diode coupled between the I/O node and an additional node, a clamp circuit coupled between the additional node and the ground node, and a clamp control circuit coupled to the clamp circuit;
- and
- a coupling circuit coupled between the additional node and the supply node including:
- a transistor coupled between the additional node and the supply node;
- a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node;
- and a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node, the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor, wherein the ESD protection unit further includes a third diode and a fourth diode coupled between the additional node and the ground node, wherein:
- the first diode includes an anode coupled to the ground node, and a cathode coupled to the I/O node;
- the second diode includes an anode coupled to the I/O node, and a cathode coupled to the additional node;
- the third diode includes an anode coupled to the ground node;
- and
- the fourth diode includes a cathode coupled to the additional node.
10 more elements
An apparatus comprising:
- a first input/output (I/O) node;
- a second I/O node;
- a first clamp circuit to turn on and form a circuit path between the first I/O node and a ground node during an electrostatic discharge (ESD) event occurred at the first I/O node;
- a second clamp circuit to turn on and form a circuit path between the second I/O node and the ground node during the ESD event;
- and
- a clamp control circuit to turn off the first and second clamp circuits at different times after the first and second clamp circuits are turned on.
3 more elements
An apparatus comprising:
- a first integrated circuit (IC) chip on a circuit board;
- a second IC chip on the circuit board and coupled to the first IC chip, at least one of the first and second IC chips including a processor;
- and at least one of the first and second IC chips including:
- a first transistor coupled between a node and a supply node, the first transistor including a gate;
- a second transistor coupled between the node and a ground node, the second transistor including a gate coupled to the gate of the first transistor;
- an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node;
- a transistor coupled between the additional node and the supply node;
- a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node;
- and
- a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node, the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor;
- and
- a connector coupled to at least one of the first and second IC chips.
9 more elements
Dependencies are inferred from the claim text.