ESD protection circuit with integral deep trench trigger diodes

An integrated circuit (IC), comprising:

• a semiconductor structure, including:
• a P-doped epitaxial layer formed above a substrate,
• a P buried layer located within the epitaxial layer,
• an N buried layer located within the P-doped epitaxial layer between the P buried layer and the substrate;
• a deep trench filled with P-doped polysilicon and extending downward through the P buried layer and the N buried layer and into the substrate between first and second regions of the semiconductor structure,
• a first deep N well extending laterally outward from at least a portion of the deep trench and downward through the P buried layer and into the N buried layer in the first region, and
• a second deep N well extending laterally outward from at least a portion of the deep trench and downward through the P buried layer and into the N buried layer in the second region;
• a protected node;
• and
• an electrostatic discharge (ESD) protection circuit, including:
• a protection transistor formed in the third epitaxial layer in the first region, including a first transistor terminal connected to the protected node, a second transistor terminal connected to a reference node, and a transistor control terminal,
• a first diode located within the first region, including a first anode connected to the transistor control terminal in the first region, and a first cathode formed by the first deep N well in the first region,
• a resistor formed between the second transistor terminal and the transistor control terminal in the first region, and
• a second diode located within the second region, including a second anode formed in the second and third epitaxial layers in the second region and connected to the first cathode, and a second cathode formed in the second deep N well in the second region and coupled with the protected node.