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US 10,319,813 B2Granted
Nanosheet CMOS transistors
AssigneeInternational Business Machines Corporation
InventorsZhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
Life of this patent
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Abstract
Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
Claims13
An integrated chip, comprising:
- a first semiconductor device in a first region, comprising:
- a plurality of vertically aligned nanosheet channels formed from a first semiconductor material;
- inner spacers formed directly between vertically adjacent nanosheet channels in the first device region;
- and
- a source and drain region formed directly on sidewalls of each of the plurality of vertically aligned nanosheet channels;
- and
- a second semiconductor device in a second region, comprising:
- a plurality of vertically aligned nanosheet channels formed from a second semiconductor material, each of the nanosheets formed from the second semiconductor material having a same height as a respective nanosheet of the first material and being formed from nanosheet layers of the first semiconductor material by a condensation process;
- inner spacers formed directly between vertically adjacent nanosheet channels in the second device region;
- and
- a source and drain region formed directly on sidewalls of each of the plurality of vertically aligned nanosheet channels.
8 more elements
Dependencies are inferred from the claim text.