Semiconductor apparatus
AssigneeSK hynix Inc.
InventorJae Seok Kang
Life of this patent
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Abstract
A semiconductor apparatus may include a first circuit forming region formed over a substrate, a first interlayer dielectric layer formed over the first circuit forming region, a first metal layer formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first metal layer, and a second circuit forming region formed over the second interlayer dielectric layer. A first circuit and a second circuit that are included in the first circuit forming region and a third circuit that is included in the second circuit forming region may be electrically coupled to each other.
Claims16
A semiconductor apparatus comprising:
- a first circuit forming region formed over a substrate;
- a first interlayer dielectric layer formed over the first circuit forming region;
- a first metal layer formed over the first interlayer dielectric layer;
- a second interlayer dielectric layer formed over the first metal layer;
- and
- a second circuit forming region formed over the second interlayer dielectric layer,
- wherein a first circuit and a second circuit that are included in the first circuit forming region and a third circuit that is included in the second circuit forming region are electrically coupled to each other,
- wherein at least one MOS (Metal-Oxide-Semiconductor) transistor is formed in the first circuit forming region,
- wherein the first circuit forming region includes the first and second circuits provided by the at least one MOS transistor, and
- wherein the second circuit forming region comprises:
- a second metal layer formed over the second interlayer dielectric layer;
- an OTS (Ovonic Threshold Switch) layer formed over the second metal layer;
- wherein the third circuit comprises an OTS transistor including a third metal layer formed over the OTS layer,
- wherein the first circuit includes a fuse array,
- wherein the second circuit includes a repair circuit, and
- wherein the third circuit includes a comparison circuit.
A semiconductor apparatus comprising:
- a first circuit forming region formed over a substrate;
- a first interlayer dielectric layer formed over the first circuit forming region;
- a first metal layer formed over the first interlayer dielectric layer;
- a second interlayer dielectric layer formed over the first metal layer;
- and
- a second circuit forming region formed over the second interlayer dielectric layer,
- a comparison circuit configured to provide a comparison result signal to the first circuit forming region in response to an address and fuse information inputted from the first circuit forming region,
- wherein the second circuit forming region comprises:
- a circuit formed of an OTS (Ovonic Threshold Switch) transistor including a second metal layer formed over the second interlayer dielectric layer, an OTS layer formed over the second metal layer, and a third metal layer formed over the OTS layer.
Dependencies are inferred from the claim text.