ESD protection circuit having clamp control loop

An integrated circuit comprising:

• a trigger circuit coupled between a first power supply bus and a second power supply bus, the trigger circuit including a first capacitive element and a first resistive element coupled in series between the first power supply bus and the second power supply bus;
• a delay circuit having an input coupled to receive an output signal from the trigger circuit and an output, the delay circuit including:
• a first inverter having an input coupled to the input of the delay circuit and an output, the first inverter including a first P-channel transistor and a first N-channel transistor coupled in series between the first power supply bus and the second power supply bus;
• a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter;
• and
• a second capacitive element having a first terminal coupled to the first power supply bus, and a second terminal coupled to the output of the first inverter;
• and
• a clamp driver circuit having an input coupled to the output of the delay circuit, and an output.