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US 10,311,194 B2Granted
Method of resolving multi-patterned color conflicts for multi-row logic cells
AssigneeSamsung Electronics Co., Ltd.
InventorsAndrew P. Hoover, Chandrakanth Ramesh, David A. Petermann
Life of this patent
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Abstract
According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.
Claims20
A method of resolving circuit design rules, the method comprising:
- accessing circuit cells from a cell library stored on a computer-readable medium;
- creating new colorable sub-portions by dividing the circuit cells into colorable sub-portions, wherein each circuit cell is associated with one or more colorable sub-portions, and wherein multi-row circuit cells include a plurality of colorable sub-portions;
- identifying a colorable sub-portion that violates a circuit design rule as a violating colorable sub-portion;
- determining that the violating colorable sub-portion is to be re-colored;
- creating a separate color swap layer, and indicating, via at least one shape of the color swap layer that the violating colorable sub-portion, but not the rest of the circuit cell, is to be at least partially re-colored, wherein re-coloring the sub-portion includes changing the color(s) of the colorable sub-portion without switching to another circuit cell;
- and
- physically generating a lithographic mask based at least the re-colored sub-portion.
4 more elements
A method comprising:
- receiving a circuit layout database that includes instantiations of circuit cells, wherein each instantiation includes one or more layout portions, wherein each layout portion is associated with a respective lithographic mask;
- creating sub-portions of each instantiation of circuit cells by dividing the respective instantiations of the circuit cells into sub-portions of uniform height, wherein each instantiation includes one or more sub-portions;
- evaluating if a design rule violation occurs between a first sub-portion and a second sub-portion;
- determining if the design rule violation is to be corrected by re-associating one or more of the layout portions of the second sub-portion with a new lithographic mask;
- if so, re-associating one or more of the layout portions of the second sub-portion with the new lithographic mask, wherein re-associating includes creating a color swap layer that identifies that the second sub-portion, and using at least in part the color swap layer, changing only the lithographic mask associated with the second sub-portion and not replacing the respective instantiation of the circuit cell with a new instantiation of the circuit cell;
- and
- physically creating the new lithographic mask.
4 more elements
A system comprising:
- a place and route tool configured to place instantiations of template circuit cells in a ordered pattern in a database of circuit layout;
- a color checker tool configured to:
- organize the instantiations by creating sub-portions from parts of respective instantiations of the template circuit cells, wherein each instantiation is associated with one or more sub-portions,
- determine if color conflicts occur between neighboring sub-portions, and
- create a separate color swap layer, and employ the color swap layer to indicate that a violating sub-portion, but not an entirety of an instantiation of the template circuit cells that is associated with the violating sub-portion, is to be re-colored, in whole or part, to correct a detected color conflict;
- and
- a mask generator configured to:
- physically generate at least two lithographic masks based upon a re-colored version of the circuit layout.
5 more elements
Dependencies are inferred from the claim text.