Full-chip hierarchical inverse lithography
AssigneeCadence Design Systems, Inc.
InventorBayram Yenikaya
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AssigneeCadence Design Systems, Inc.
InventorBayram Yenikaya
Estimating the term…
According to certain aspects, the present embodiments relate to an inverse lithography technology (ILT) solution that provides masks with perfect symmetry and minimal complexity. A methodology according to the embodiments includes several steps and strictly maintains symmetry in each of these steps. In one step, lithographic model kernels are processed to enforce symmetry corresponding to an illumination source. In another step, an ideal grayscale mask for a target pattern is computed using the symmetrical model kernels and computation domain centered on each target polygon. In another step optimized polygons are computed using the computed grayscale mask. The final mask perfectly maintains the symmetry properties of the illumination source. An ILT solution according to the embodiments can be used on an original design hierarchy and on a full chip scale.
A method of obtaining a mask pattern for printing a target pattern using an optical system, comprising:
A computer readable storage medium comprising instructions recorded thereon, the instructions, when executed by a computer, cause the computer to perform a method of obtaining a mask pattern for printing a target pattern using an optical system, the method comprising:
A system for obtaining a mask pattern for printing a target pattern using an optical system, comprising:
Dependencies are inferred from the claim text.