H04L 27/2272
Using phase locked loops
Official title: {using phase locked loops (H04L27/2273 takes precedence)}
H04L27/2272 (Using phase locked loops) appears on 159 US grants and 81 published applications in this corpus.
Search patents in H04L- Granted patents
- 159
- Published applications
- 81
- Assignees
- 105
- Inventors
- 270
- Latest grant
- 12 Aug 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 4 | 0 |
| 1978 | 4 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 1 | 0 |
| 1982 | 3 | 0 |
| 1983 | 5 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 7 | 0 |
| 1988 | 3 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 2 | 0 |
| 1998 | 2 | 0 |
| 1999 | 4 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 3 |
| 2002 | 0 | 3 |
| 2003 | 0 | 3 |
| 2004 | 5 | 4 |
| 2005 | 5 | 2 |
| 2006 | 5 | 1 |
| 2007 | 3 | 2 |
| 2008 | 3 | 4 |
| 2009 | 1 | 0 |
| 2010 | 4 | 3 |
| 2011 | 4 | 3 |
| 2012 | 4 | 5 |
| 2013 | 3 | 6 |
| 2014 | 10 | 4 |
| 2015 | 6 | 6 |
| 2016 | 3 | 2 |
| 2017 | 6 | 6 |
| 2018 | 7 | 2 |
| 2019 | 8 | 11 |
| 2020 | 4 | 4 |
| 2021 | 6 | 3 |
| 2022 | 1 | 2 |
| 2023 | 3 | 0 |
| 2024 | 1 | 1 |
| 2025 | 1 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Hybrid clocking scheme for SERDES physical layer circuits12 Aug 2025US 12,388,692 B2QUALCOMM Incorporated
- Time-to-digital converter apparatus and converting method thereof29 Oct 2024US 12,130,592 B2Nanya Technology Corporation
- Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence12 Sep 2023US 11,757,609 B2Marvell Asia Pte Ltd
- Channel equalization14 Mar 2023US 11,606,230 B2Apple Inc.
- Power saving by combining multiple bandwidth parts (BWPs) into a single wideband channel14 Feb 2023US 11,582,751 B2QUALCOMM Incorporated
- Hybrid clocking scheme for serdes physical layer circuits15 May 2025US 2025/0158858 A1QUALCOMM Incorporated
- Time-to-digital converter apparatus and converting method thereof11 Jul 2024US 2024/0231281 A1Nanya Technology Corporation
- Power saving by combining multiple bandwidth parts (bwps) into a single wideband channel22 Sep 2022US 2022/0303990 A1QUALCOMM Incorporated
- Channel equalization8 Sep 2022US 2022/0286334 A1Apple Inc.
- Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence2 Sep 2021US 2021/0273776 A1Marvell Asia Pte Ltd
Most cited
By later US patents
- System for remote data collection172US 6,163,276 ACellNet Data Systems, Inc. · 2000
- High speed data communication system using phase shift key coding106US 5,185,765 A1993
- High speed binary data communication system99US 4,742,532 A1988
- Doppler frequency compensation circuit78US 5,063,387 AUnisys Corporation · 1991
- N-phase modulated signal demodulation system with carrier reproduction66US 5,614,861 AMitsubishi Denki Kabushiki Kaisha · 1997