G06F 2212/272
Cache only memory architecture [coma]
Official title: Cache only memory architecture [COMA]
G06F2212/272 (Cache only memory architecture [coma]) appears on 50 US grants and 19 published applications in this corpus.
Search patents in G06F- Granted patents
- 50
- Published applications
- 19
- Assignees
- 20
- Inventors
- 69
- Latest grant
- 17 Jun 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 6 | 0 |
| 1999 | 6 | 0 |
| 2000 | 3 | 0 |
| 2001 | 6 | 2 |
| 2002 | 6 | 4 |
| 2003 | 6 | 4 |
| 2004 | 2 | 0 |
| 2005 | 1 | 1 |
| 2006 | 0 | 0 |
| 2007 | 1 | 1 |
| 2008 | 1 | 1 |
| 2009 | 0 | 1 |
| 2010 | 0 | 0 |
| 2011 | 1 | 1 |
| 2012 | 0 | 1 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 1 |
| 2018 | 0 | 1 |
| 2019 | 1 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 1 |
| 2025 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Storage module supporting single serialized write interfacing scheme and operation method thereof17 Jun 2025US 12,332,797 B2Samsung Electronics Co., Ltd.
- Techniques for managing memory in a multiprocessor architecture23 Jul 2019US 10,360,150 B2Suse LLC
- Cache memory for a scalable information distribution system28 Jun 2011US 7,970,999 B2ARRIS Group, Inc.
- Cache memory for a scalable information distribution system18 Mar 2008US 7,346,738 B2Broadband Royalty Corporation
- Cache memory for a scalable information distribution system3 Apr 2007US 7,200,718 B2Broadband Royalty Corporation
- Storage module supporting single serialized write interfacing scheme and operation method thereof18 Jan 2024US 2024/0020234 A1Samsung Electronics Co., Ltd.
- Method and apparatus for data access in storage system21 Jun 2018US 2018/0173624 A1EMC IP Holding Company LLC
- Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system28 Dec 2017US 2017/0371783 A1QUALCOMM Incorporated
- Techniques for managing memory in a multiprocessor architecture16 Aug 2012US 2012/0210065 A1Suse LLC
- Systems and methods for managing large cache services in a multi-core system23 Jun 2011US 2011/0153953 A1
Most cited
By later US patents
- Multiprocessor digital data processing system129US 5,055,999 AKendall Square Research Corporation · 1991
- Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes116US 5,887,138 ASun Microsystems, Inc. · 1999
- Dynamic packet routing network114US 5,282,201 AKendall Square Research Corporation · 1994
- Shared memory multiprocessor system and method of operation thereof88US 5,297,265 AKendall Square Research Corporation · 1994
- High-speed packet switching apparatus and method83US 5,335,325 AKendall Square Research Corporation · 1994