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US RE48,735 E1Granted
Use of a recirculating delay line with a time-to-digital converter
AssigneeSilicon Laboratories Inc.
InventorRaghunandan Kolar Ranganathan
Life of this patent
Estimating the term…
Abstract
The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.
Claims20
A method for performing a time to digital conversion comprising:
- receiving an input pulse indicative of time information;
- recirculating a representation of the input pulse in at least one delay line;
- generating an output pulse corresponding to the input pulse based, at least in part, on a delay line output signal of the at least one delay line;
- and
- supplying the output pulse N times to an integrator, where N is an integer greater than one.
2 more elements
An apparatus comprising:
- a delay line;
- input logic coupled to receive an input pulse and coupled to receive an output of the delay line, the input logic to supply a delay line input signal to the delay line, wherein a representation of the input pulse is recirculated in the delay line;
- and
- an integrating time to digital converter coupled to the delay line to receive N pulse out signals, each pulse out signal corresponding to the input pulse to thereby generate a digital representation of the input pulse multiplied by a gain of N, where N is an integer greater than one.
1 more element
An apparatus comprising:
- a delay line supplying a delay line output signal;
- a rising edge detector to detect a rising edge of an input pulse and supply a rising edge pulse;
- a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse;
- a first logic circuit to logically combine the rising edge pulse, the falling edge pulse, and a feedback signal based on the delay line output signal;
- and
- a second logic circuit coupled to receive an enable signal and an output pulse based on the delay line output signal and to pass the output pulse when the enable signal is asserted.
3 more elements
Dependencies are inferred from the claim text.