Semiconductor memory device and related method of programming

A method of programming a nonvolatile memory device, comprising:

• applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;
• performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;
• applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation;
• and
• based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,
• wherein the second region has a threshold voltage range between the first region and the third region;
• the verify voltage and the pre-charging voltage is maintained constantly during the verify operation regardless of the result of the first verify operation, and
• the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.

A method of programming a nonvolatile memory device, comprising:

• applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;
• performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region, and the verify operation including a first verify operation and a second verify operation following the first verify operation;
• applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation;
• and
• applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region, the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a power supply voltage, and the first memory cell being sensed as off-cell at the first verify operation and sensed as on-cell at the second verify operation;
• wherein the at least two different times include a first time for a first sense node develop operation of the first verify operation and a second time for a second sense node develop operation of the second verify operation, the first time being shorter than the second time,
• the second region has a threshold voltage range between the first region and the third region;
• the verify voltage and the pre-charging voltage is maintained constantly during the verify operation regardless of a result of the first verify operation.

A method of programming a nonvolatile memory device, comprising:

• performing a first program loop including:
• applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;
• and
• performing a verify operation by applying a verify voltage to the selected wordline to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, and
• performing a second program loop after the first program loop, the second program loop including:
• applying a second program voltage higher than the first program voltage to the selected wordline;
• and
• based on a result of the verify operation, applying a bit-line voltage to a first bitline connected to a first memory cell during the applying the second program voltage to the selected wordline, the bit-line voltage being higher than a ground voltage and lower than a program-inhibit voltage,
• wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges,
• the at least two different times include a first time for the first verify operation and a second time for the second verify operation, the first time being different from the second time,
• the at least three regions include a first region, a second region and a third region, the second region having a higher threshold voltage range than the first region, the second region having a lower threshold voltage range than the third region, and
• the verify voltage is maintained at a constant level during the verify operation, the verify operation including:
• applying a pre-charging voltage to a first bitline among selected bitlines connected to the selected memory cells;
• performing a first develop operation of a sense node while the sense node and the first bitline are coupled together during the first time;
• and
• performing a first sensing operation to a first memory cell connected to the first bitline by sensing a first developed voltage of the sense node after the performing the first develop operation;
• after the performing the first sensing operation, performing a second develop operation of the sense node while the sense node and the first bitline are coupled together during the second time;
• and
• performing a second sensing operation to the first memory cell connected to the first bitline by sensing a second developed voltage of the sense node after the performing the second develop operation,
• wherein the pre-charging voltage is maintained at a constant level during the verify operation regardless of a result of the first sensing operation,
• the first memory cell is included in the second region, and
• the first memory cell is sensed as off-cell at the first sensing operation and sensed as on-cell at the second sensing operation.

A method of programming a nonvolatile memory device, comprising:

• applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;
• performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;
• applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation;
• and
• based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,
• wherein the second region has a threshold voltage range between the first region and the third region;
• the pre-charging voltage is maintained constantly during the verify operation regardless of the result of the first verify operation, and
• the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.

A method of programming a nonvolatile memory device, comprising:

• applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;
• performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;
• applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation;
• and
• based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,
• wherein the second region has a threshold voltage range between the first region and the third region;
• the pre-charging voltage is not discharged during the verify operation regardless of the result of the first verify operation, and
• the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.