Verification circuits and methods for phase change memory array

A verification method for a phase change memory array, comprising:

• providing a writing current to a first memory cell of the phase change memory array and gradually increasing the writing current until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage;
• recording the current magnitude of the writing current as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage;
• reading a second memory cell of the phase change memory array to obtain a second sensing voltage;
• determining whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage;
• and
• providing the writing current with the reference current magnitude to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state.

A method, comprising:

• increasing a writing current applied to a first memory cell of a non-volatile memory until a first sensing voltage is larger than or equal to a reference voltage;
• identifying a magnitude of the writing current as a reference current magnitude;
• determining that a second memory cell of the non-volatile memory is in a non-reset state by comparing a second sensing voltage and the reference voltage;
• and
• providing the writing current with the reference current magnitude to the second memory cell in response to said determining.

A circuit, comprising:

• a sensing unit configured to identify a sensing voltage associated with a first memory cell of a non-volatile memory;
• a writing current generator configured to increase a writing current applied to the first memory cell until the first sensing voltage is larger than or equal to a reference voltage, wherein a magnitude of the writing current is configured to be identified as a reference current magnitude;
• and
• a comparator configured to compare a second sensing voltage and the reference voltage, wherein the writing current with the reference current magnitude is applied to a second memory cell of the non-volatile memory in response to determining that the second memory cell is in a non-reset state.