Integrated digital signal processing circuit for performing cosine transformation
AssigneeSGS-Thomson Microelectronics S.A.
InventorJoel Cambonie
Life of this patent
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Abstract
Integrated circuits capable of carrying out transformations of the "cosine transformation" type, used more particularly for the digital processing of images with a view to information compression. The versatile and compact circuit architecture involves dividing a bus into sections separated by switches actuated in phase opposition; certain sections are coupled to computing operators, whereas others are coupled to memories serving for reorganizing the order in which the data is presented to the following operators.
Claims23
An integrated circuit for the digital processing of signals, performing a specific transformation of input signals representing a digital values x.sub.j so as to produce signals representing n coefficients F.sub.v of the form ##EQU2## wherein f(j,v) is a function of the indexes j and v, comprising:
- a signal transmission bus for unidirectionally transmitting a signal of p bits representing a digital value;
- switches spaced apart along the bus for letting the signals pass along the bus or for interrupting these signals, with any two adjacent switches along the bus being actuated in phase opposition, so as to divide the bus into sections, each bus section communicating alternately with a preceding section and a following section;
- computing operators are connected to certain sections of the bus and may receive successive data of p bits therefrom, for carrying out a computation on this data and sending resulting data over this bus section;
- buffer memories are connected to other bus sections so as to receive several successive data therefrom and send them over a bus in an order different from the order in which they were received;
- microprogrammed sequences for controlling each of said computation operator or said buffer memory.
An integrated circuit for the digital processing of signals, performing a specific transformation of input signals representing n coefficients F.sub.v so as to produce signals representing n digital values X.sub.j wherein the relationship of F.sub.v and X.sub.j is of the form ##EQU3## and wherein f(j,v) is a function of the indexes j and v, the circuit comprising:
- a signal transmission bus for unidirectionally transmitting a signal of p bits representing a digital value;
- switches spaced apart along the bus for letting the signals pass between the bus or for interrupting these signals, with any two adjacent switches along the bus being actuated in phase opposition, so as to divide the bus into sections, each bus section communicating alternately with a preceding section and a following section;
- computing operators are connected to certain sections of the bus and may receive successive data of p bits therefrom, for carrying out a computation on this data and sending resulting data over this bus section;
- buffer memories are connected to other bus sections so as to receive several successive data therefrom and send them over a bus in an order different from the order in which they were received;
- and
- a sequencer for controlling said computing operators and said buffer
- memories.
An integrated circuit for the digital processing of signals, performing specific transformation of input signals representing n digital values X.sub.j so as to produce signals representing n coefficients F.sub.v of the form ##EQU4## wherein f(j,v) is a function of the indexes j and v, comprising:
- a signal transmission bus for unidirectionally transmitting a signal of p bits representing a digital value;
- switches spaced apart along the bus for letting the signals pass along the bus or for interrupting these signals, with any two adjacent switches along the bus being actuated in phase opposition, so as to divide the bus into sections, each bus section communicating alternately with a preceding section and a following section;
- computing operators are connected to certain sections of the bus and may receive successive data of p bits therefrom, for carrying out a computation on this data and sending resulting data over this bus section;
- buffer memories are connected to other bus sections so as to receive several successive data therefrom and send them over to a bus in an order different from the order in which they were received;
- and
- a sequencer for controlling said computing operators and said buffer
- memories.
An integrated circuit for the digital processing of signals, performing specific transformation between signals representing n digital values X.sub.j and n coefficients F.sub.v of the form ##EQU5## wherein f(j,v) is a function of the indexes j and v, comprising:
- a signal transmission bus for unidirectionally transmitting a signal of p bits representing a digital value;
- switches spaced apart along the bus for letting the signals pass along the bus or for interrupting these signals, with any two adjacent switches along the bus being actuated in phase opposition, so as to divide the bus into sections, each bus section communicating alternately with a preceding section and a following section;
- computing operators are connected to certain sections of the bus and may receive successive data of p bits therefrom, for carrying out a computation on this data and sending resulting data over this bus section;
- buffer memories are connected to other bus sections so as to receive several successive data therefrom and send them over to a bus in an order different from the order in which they were received;
- and
- a sequencer for controlling said computing operators and said buffer memories.
Dependencies are inferred from the claim text.