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US RE31,311 EGranted
DC Free encoding for data transmission system
AssigneeAmpex Corporation
InventorJerry W. Miller
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AssigneeAmpex Corporation
InventorJerry W. Miller
Estimating the term…
A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by producing a first indicating signal, and in response to the first indicating signal and the state of a current bit and the state of the next succeeding bit the transmission of signal transitions is modified to eliminate any DC component. Preferably, the end of a sequence of second bit states that would introduce a DC component is detected by producing a second indicating signal utilized to modify the signal transitions at the end of a troublesome sequence, as by suppressing the transition corresponding to the last second bit state in such a sequence.
In a self-clocking transmission system for transmitting binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in [the] respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any [transitions] transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to bit states for producing at the onset of a sequence of second bit states following a first bit state a first indicating signal indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, and means responsive to said first indicating signal, a current bit and but one next succeeding bit for modifying the transmission of signal transitions to eliminate any DC [components] component.
In a self-clocking transmission system for transmitting binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in [the] respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in [the] respective bit cells and any transition relatively early in a bit-cell following a transition relatively late in the next preceding bit cell is suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to bit states for producing at the onset of a sequence of second bit states following a first bit state a first indicating signal indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to said first signal and to but one bit next succeeding a current bit for producing a second indicating signal indicating the end of a sequence of second bit states that would introduce a DC component into the transmitted signal with normal transmission, and means responsive to said second indicating signal for modifying the transmission of signal transitions at the end of such a sequence to eliminate any DC component.
In a self-clocking transmission system for transmitting binary data sequentially in successive [clock] clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in respective bit cells, logical second bit states are normally transmitted at signal transitions relatively late in [the] respective bit cells, any transition corresponding to a first bit state following a second bit state is suppressed, and certain transitions corresponding to second bit states preceding the first bit states are suppressed, decoding apparatus responsive to transmited signal transitions for indicating the bit state of the binary data transmitted, said decoding apparatus comprising synchronizing means responsive to transmitted signal transitions for providing timing signals for distinguishing relatively early transitions from relatively late transitions, detection means responsive to said transmitted signal transitions and said timing signals for indicating first bit states upon receipt of relatively early transitions and second bit states upon receipt of relatively late transitions, suppressed transition detection means responsive to said transmitted signal transitions and said timing signals for detecting the absence of a transition within 21/2 bit cells following a relatively late transition by producing a suppressed transition detection signal [and] means responsive to said suppressed transition detection signal for indicating the bit following that corresponding to the transition preceding said 21/2 bit cells as in the second bit state, and means responsive to said timing signals for indicating any other bit as in the first bit state.
A self-clocking method for transmitting binary data sequentially in successive [clock] clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted [by] as signal transitions relatively early in respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a DC component to the transmitted signal with normal transmission by producing a first indicating signal indicating any such sequence, and in response to said first indicating signal and the state of a current bit and the state of the next succeeding bit modifying the transmission of signal transitions to eliminate any DC component.
A self-clocking method for transmitting binary data sequentially in successive [clock] clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in [the] respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in [the] respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission by producing a first indicating signal indicating any such sequence, and in response to said first indicating signal and to the state of the next succeeding bit detecting the end of a sequence of second bit states that would introduce a DC component into the transmitted signal with normal transmission by producing a second indicating signal indicating any such sequence that would introduce a DC component, and in response to said second indicating signal modifying the transmission of signal transitions at the end of such a sequence to eliminate any DC component.
In a self-clocking method for transmitting binary data sequentially in successive [clock] clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in respective bit cells, logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells, any transitions corresponding to a first bit state following a second bit state is suppressed, and certain transitions corresponding to second bit states preceding first bit states are suppressed, a method of decoding the transmitted signal comprising deriving a timing signal from the transmitted data signal transitions for distinguishing relatively early and relatively late transitions, indicating first bit states upon relatively early transitions and second bit states upon relatively late transitions, detecting a suppressed relatively late transition by the absence of a transition within 2 and a fraction bit cells subsequent to a relatively late transition, [and] indicating a second bit state upon the detection of a suppressed relatively late transition, and indicating a first bit state in the absence of a transition in any other respective bit cell.
Dependencies are inferred from the claim text.