Circuit and method for creating additional data transitions

A system comprising:

• a first multiplexer to multiplex a pair of half-rate data signals to produce a first full-rate data signal;
• first CMOS circuitry to receive the first full-rate data signal;
• an inverter to invert one of the pair of half-rate data signals to produce an inverted half-rate data signal, and a second multiplexer to multiplex the inverted half-rate data signal with the other one of the pair of half-rate data signals to produce a second full-rate data signal;
• and
• second CMOS circuitry to receive the second full-rate data signal in parallel to the first CMOS circuitry receiving the first full-rate data signal to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period, the first CMOS circuitry and the second CMOS circuitry being connected to a same power supply, and the second CMOS circuitry being substantially the same as the first CMOS circuitry,
• wherein the system is part of:
• a serialize/deserialize (SERDES) receiver or transmitter, or an advanced modulation receiver or transmitter, or a clock/data recover (CDR) device, or a CMOS transimpedance amplifier (TIA) circuit, or a CMOS laser driver, or an analog to digital converter (ADC) circuit.

A method in a transmitter, the method comprising:

• receiving a first data signal representing a plurality of bits at first CMOS circuitry;
• generating a second data signal so that the second data signal is a version of the first data signal with every second bit of the plurality of bits inverted;
• and
• receiving the second data signal at second CMOS circuitry in parallel to receiving the first data signal at the first CMOS circuitry to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits, the first CMOS circuitry and the second CMOS circuitry being connected to a same power supply.