Three-dimensional semiconductor memory device and method of fabricating the same

A semiconductor memory device, comprising:

• a stack including gate electrodes sequentially stacked on a substrate;
• a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes;
• a vertical channel portion disposed on an inner surface of the vertical insulating structure;
• a lower channel penetrating a lower portion of the stack and disposed between the vertical channel portion and the substrate;
• a capping pattern disposed in an inner space surrounded by the vertical channel portion;
• and
• a common source region formed in the substrate and spaced apart from the vertical channel portion,
• wherein the lower channel includes an uppermost surface and top surfaces positioned at both sides of the uppermost surface, and the top surfaces are gradually inclined with respect to a top surface of the substrate,
• wherein a bottom surface of the vertical insulating structure is gradually inclined with respect to the top surface of the substrate, and
• wherein the capping pattern has a width varying depending on a distance from the lower channel.