Differential odd integer divider
AssigneeTexas Instruments Incorporated
InventorSudipto Chakraborty
Life of this patent
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Abstract
A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.
Claims3
A circuit for performing odd-integer frequency division of a first clock signal, having a set of six-transistor delay cells connected in a ring with an output of one six-transistor delay cell electrically connected to an input of a next six-transistor delay cell in the ring, wherein each six-transistor delay cell comprises:
- a first transistor having a first control terminal connected to a second output terminal and having a first current path connected between a first power supply terminal and a first output terminal;
- a second transistor having a second control terminal connected to the first output terminal and having a second current path connected between the first power supply terminal and the second output terminal;
- a third transistor having a third control terminal connected to a first output terminal of a previous six-transistor delay cell and having a third current path connected between the first output terminal of the respective six-transistor delay cell and a second power supply terminal;
- a fourth transistor having a fourth control terminal connected to a second output terminal of the previous six-transistor delay cell and having a fourth current path connected between the second output terminal of the respective six-transistor delay cell and the second power supply terminal;
- a fifth transistor having a fifth control terminal coupled to receive the first clock signal and having a fifth current path connected in series with the third current path;
- and
- a sixth transistor having a sixth control terminal coupled to receive a second clock signal and having a sixth current path connected in series with the fourth current path, wherein the circuit produces an output signal having a frequency of the first clock signal divided by an odd integer equal to a number of six-transistor delay cells in the set;
- and
- a controller configured to bypass individual ones of the set of six-transistor delay cells.
A circuit for performing odd-integer frequency division of a first clock signal, having a set of six-transistor delay cells connected in a ring with an output of one six-transistor delay cell electrically connected to an input of a next six-transistor delay cell in the ring, wherein each six-transistor delay cell comprises:
- a first transistor having a first control terminal connected to a second intermediate terminal and having a first current path connected between a first power supply terminal and a first intermediate terminal;
- a second transistor having a second control terminal connected to the first intermediate terminal and having a second current path connected between the first power supply terminal and the second intermediate terminal;
- a third transistor having a third control terminal connected to a first intermediate terminal from a previous six-transistor delay cell and having a third current path connected between the first intermediate terminal of the respective six-transistor delay cell and a second power supply terminal;
- a fourth transistor having a fourth control terminal connected to a second intermediate terminal from the previous six-transistor delay cell and having a fourth current path connected between the second intermediate terminal of the respective six-transistor delay cell and the second power supply terminal;
- a fifth transistor having a fifth control terminal coupled to receive the first clock signal and having a fifth current path connected in series with the third current path;
- and
- a sixth transistor having a sixth control terminal coupled to receive a second clock signal and having a sixth current path connected in series with the fourth current path, wherein the circuit produces an output signal having a frequency of the first clock signal divided by an odd integer equal to a number of six-transistor delay cells in the set;
- and
- a controller configured to bypass individual ones of the set of six-transistor delay cells to perform the odd-integer frequency division.
A method of performing odd-integer frequency division of a first clock signal with a set of six-transistor delay cells connected in a ring with an output of one six-transistor delay cell electrically connected to an input of a next six-transistor delay cell in the ring, comprising:
- receiving a first input signal at a first input transistor of a first six-transistor delay cell from a previous six-transistor delay cell;
- receiving a second input signal at a second input transistor of the first six-transistor delay cell from the previous six-transistor delay cell;
- forming a first current path from the first input transistor to a second power supply terminal in response to the first clock signal;
- forming a second current path from the second input transistor to the second power supply terminal in response to a second clock signal;
- and
- latching the first and second input signals from the respective first and second input transistors in a latch formed only by a first switch transistor and a second switch transistor connected to a first power supply terminal in response to the first and second input signals and the first and second clock signals, wherein the method produces an output signal having a frequency of the first clock signal divided by an odd integer equal to a number of six-transistor delay cells in the set;
- and
- selectively bypassing individual ones of the set of six-transistor delay cells to perform the odd-integer frequency division.
Dependencies are inferred from the claim text.