Frequency divider and phase-locked loop including the same

A phase-locked loop including a frequency divider, wherein the frequency divider comprises:

• a first shifter comprising first to M-th clock control components connected together to form a first ring, wherein the control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring, wherein M is a first integer greater than one, and wherein an output of selected clock control components in the first shifter is provided as a carry signal of the first shifter;
• a second shifter comprising first to N-th clock control components connected together to form a second ring, wherein the control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring, wherein N is a second integer greater than one, and wherein an output of selected clock control components in the second shifter is provided as a carry signal of the second shifter;
• and
• a selection module configured to:
• receive the output of each clock control component in the first shifter and the second shifter;
• and,
• based on a division factor:
• provide the output of selected clock control components in the first shifter as the carry signal of the first shifter to the second shifter, and the output of selected clock control components in the second shifter as the carry signal of the second shifter,
• wherein the selection module comprises an AND gate having a first input, a second input, and an output,
• wherein the carry signal of the first shifter is connected to the first input of the AND gate, and the carry signal of the second shifter is connected to the second input of the AND gate, and
• wherein the output of the AND gate is the output of the selection module.

A method of operating a frequency divider, wherein the frequency divider comprises a first shifter comprising first to M-th clock control components connected together to form a first ring, a second shifter comprising first to N-th clock control components connected together to form a second ring, wherein M is a first integer greater than one and N is a second integer greater than one, and a selection module comprising an AND gate having a first input, a second input, and an output, the method comprising:

• controlling the first shifter using an input clock signal such that signals are shifted along the first ring;
• providing the output of selected clock control components in the first shifter as a carry signal of the first shifter;
• controlling the second shifter using the carry signal of the first shifter such that the signals are shifted along the second ring;
• providing the output of selected clock control components in the second shifter as a carry signal of the second shifter;
• providing the carry signal of the first shifter to the first input of the AND gate;
• and
• providing the carry signal of the second shifter to the second input of the AND gate.