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US 9,900,014 B2Granted
Frequency dividing circuit and semiconductor integrated circuit
AssigneeSocionext Inc.
InventorTetsuro Tamura
Life of this patent
Estimating the term…
Abstract
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.
Claims13
A frequency dividing circuit comprising:
- a plurality of latch circuits that include a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the plurality of latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit;
- and
- a generation circuit configured to generate each of a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of a pair of a first latch circuit driven at the rising of the clock signal and a second latch circuit driven at the falling of the clock signal, the first latch circuit and the second latch circuit being adjacent to each other, among the plurality of latch circuits.
A semiconductor integrated circuit comprising:
- a plurality of latch circuits that include a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit;
- a generation circuit configured to generate each of a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of a pair of a first latch circuit driven at the rising of the clock signal and a second latch circuit driven at the falling of the clock signal, the first latch circuit and the second latch circuit being adjacent to each other, among the plurality of latch circuits;
- and
- a conversion circuit configured to serial-parallel convert and output inputted serial data based on the plurality of frequency divided clock signals.
1 more element
A semiconductor integrated circuit comprising:
- a plurality of latch circuits that includes a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit;
- a generation circuit configured to generate each of a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of a pair of a first latch circuit driven at the rising of the clock signal and a second latch circuit driven at the falling of the clock signal, the first latch circuit and the second latch circuit being adjacent to each other among, the plurality of latch circuits;
- and
- a conversion circuit configured to parallel-serial convert and output inputted parallel data based on the plurality of frequency divided clock signals.
1 more element
Dependencies are inferred from the claim text.