Substrate structure for packaging chip

A manufacturing method of a substrate structure, comprising:

• providing a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region;
• forming a plurality of through holes in the packaging region;
• providing a carrier, wherein the carrier comprises a release layer, a dielectric layer, and a metal layer, the dielectric layer being disposed between the release layer and the metal layer;
• laminating the substrate to the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier;
• packaging a chip on the packaging region of the substrate, wherein the chip directly contacts the release layer filled into the through holes;
• and
• separating the chip and the substrate from the release film and the carrier to expose the back surface of the chip after packaging the chip on the substrate.