Timing based corrector for video
AssigneeLattice Semiconductor Corporation
InventorsGenlin Liu, Bing Zhang
Life of this patent
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Abstract
A device that stabilizes video timing signals from an analog video signal is provided. In one embodiment, such a device includes a video PLL controller and a vertical synchronization (Vsync) signal generator. The device output a clock for digital video data, where the clock follows the Vsync signal from the analog video but within the jitter requirements for the clock.
Claims19
A device for generating an output vertical synchronization (Vsync) signal based on an input Vsync signal of an analog video signal, subject to jitter requirements on an output video clock signal based on the output Vsync signal, the device comprising:
- a phase frequency detector configured to generate a phase difference between the input Vsync signal and the output Vsync signal;
- a digital filter configured to filter the phase difference to produce a Vsync adjustment signal;
- a limiter module configured to limit the Vsync adjustment signal such that the output video clock signal is compliant with the jitter requirements;
- and
- a Vsync generator configured to adjust timing of the output Vsync signal to follow the input Vsync signal based on the limited Vsync adjustment signal.
Dependencies are inferred from the claim text.