System and method for enhanced channel estimation using tap-dependent frequency offset (FO) estimation

A phase locked loop (PLL), comprising:

• a per-tap phase detector which receives an lth orthogonal frequency division multiplexing (OFDM) symbol, processes each tap i of the lth OFDM symbol, and produces a per-tap phase value for each tap i of the lth OFDM symbol;
• an adder which sums all of the per-tap phase values of the lth OFDM symbol;
• a loop filter which filters the sum of all of the per-tap phase values of the lth OFDM symbol to generate an output;
• and
• a voltage-controlled oscillator (VCO) which receives the output of the loop filter and generates the output of the PLL, which is also used as input to the per-tap phase detector in a feedback loop.

A method of operation of a phase locked loop (PLL) in an apparatus capable of channel estimation in a high speed single frequency network (HS-SFN), comprising:

• receiving an lth orthogonal frequency division multiplexing (OFDM) symbol;
• determining a number K of taps of the lth OFDM symbol, where i=0, 1, 2, . . . , K−1;
• processing each tap i of the lth OFDM symbol and producing a per-tap phase value for each tap i of the lth OFDM symbol;
• obtaining a sum of all of the per-tap phase values of the lth OFDM symbol;
• filtering the sum of all of the per-tap phase values of the lth OFDM symbol;
• and
• generating a channel estimation based at least on the filtered sum of all of the per-tap phase values of the lth OFDM symbol, wherein the generated channel estimation is also used in the steps of processing and producing per-tap phase values for each tap i of the (l+1)th OFDM symbol as part of a feedback loop.

A chip capable of channel estimation in a high speed single frequency network (HS-SFN), comprising:

• at least one non-transitory computer-readable medium;
• and
• at least one processor, which, when executing instructions stored on one or more of the at least one non-transitory computer-readable medium, has the chip perform at least the following steps:
• calculating an estimated frequency offset (FO) correction for a received signal using at least an FO estimation generated by an automatic frequency control (AFC) module using at least a previously-calculated channel estimate output from a channel estimator (CE) as input in a first feedback loop;
• and
• calculating, by the CE, a current channel estimate using at least the received signal adjusted by the estimated FO correction from the first feedback loop and one or more channel parameter estimates generated by the AFC using at least the previously-calculated channel estimate output from the CE as input in a second feedback loop.

A method of manufacturing a chip capable of channel estimation in a high speed single frequency network (HS-SFN), comprising:

• forming at least one non-transitory computer-readable medium disposed as part of the chip;
• and
• forming at least one processor disposed as part of the chip,
• wherein the at least one processor, when executing instructions stored on one or more of the at least one non-transitory computer-readable medium, has the chip perform at least the following steps:
• calculating an estimated frequency offset (FO) correction for a received signal using at least an FO estimation generated by an automatic frequency control (AFC) module using at least a previously-calculated channel estimate output from a channel estimator (CE) as input in a first feedback loop;
• and
• calculating, by the CE, a current channel estimate using at least the received signal adjusted by the estimated FO correction from the first feedback loop and one or more channel parameter estimates generated by the AFC using at least the previously-calculated channel estimate output from the CE as input in a second feedback loop.