Device including single wire interface and data processing system including the same

A data processing system comprising:

• a master device including:
• a first single pad;
• a first control circuit;
• a first frame generator configured to generate a first frame for based on a control of the first control circuit;
• and
• a first processing circuit configured to generate a first oversampling clock signal from a first clock signal, configured to select one among a plurality of first clock phases of the first oversampling clock signal, and configured to sample a bit value included in a second frame using the same phase as the selected one among the plurality of first clock phases;
• a slave device including:
• a second single pad;
• a second control circuit;
• a second frame generator configured to generate the second frame for data transmission based on a control of the second control circuit;
• and
• a second processing circuit configured to generate a second oversampling clock signal from a second clock signal, configured to select one among a plurality of second clock phases of the second oversampling clock signal, and configured to sample a bit value included in the first frame using the same phase as the selected one among the plurality of second clock phases;
• a first clock source configured to provide the first clock signal to the master device;
• a second clock source configured to provide the second clock signal to the slave device;
• and
• a single wire through which the master device communicates with the slave device, the single wire being connected between the first single pad and the second single pad,
• wherein the single wire is bidirectional,
• the first frame is transmitted from the master device to the slave device, and
• the second frame is transmitted from the slave device to the master device.

A data processing system comprising:

• a master device including:
• a first single pad;
• a first control circuit;
• a first frame generator configured to generate a first frame for based on a control of the first control circuit;
• and
• a first processing circuit configured to generate a first oversampling clock signal from a first clock signal, configured to select one among a plurality of first clock phases of the first oversampling clock signal, and configured to sample a bit value included in a second frame using the same phase as the selected one among the plurality of first clock phases;
• a slave device including:
• a second single pad;
• a second control circuit;
• a second frame generator configured to generate the second frame for data transmission based on a control of the second control circuit;
• and
• a second processing circuit;
• and
• a single wire through which the master device communicates with the slave device, the single wire being connected between the first single pad and the second single pad,
• wherein the single wire is bidirectional,
• the first frame is transmitted from the master device to the slave device,
• the second frame is transmitted from the slave device to the master device, and
• the second processing circuit includes:
• a clock generator configured to generate a second oversampling clock signal from a second clock signal;
• a sync detection circuit configured to select one among a plurality of second clock phases of the second oversampling clock signal;
• a data processing circuit configured to sample a bit value included in the first frame using the same phase as the selected one among the plurality of second clock phases;
• and
• an enable signal generator configured to generate an enable signal that controls a transmission of the second clock signal into the clock generator.

A device comprising:

• a single pad;
• a control circuit;
• a frame generator configured to generate a first frame for data transmission based on a control of the control circuit;
• and
• a processing circuit;
• and
• a single wire through which the first frame for the data transmission is transmitted to an external device,
• wherein the single wire is bidirectional and is connected to the single pad, and
• the processing circuit includes:
• a clock generator configured to generate an oversampling clock signal from a clock signal;
• a sync detection circuit configured to select one among a plurality of clock phases of the oversampling clock signal;
• a data processing circuit configured to sample a bit value included in a second frame using the same phase as the selected one among the plurality of clock phases, the second frame being received from the external device via the single wire;
• and
• an enable signal generator configured to generate an enable signal that controls a transmission of the clock signal into the clock generator.

A method of performing communications between a master device and a slave device, the method comprising:

• communicating a frame between the master device and the slave device via only one asynchronous wire;
• generating an oversampling clock signal;
• selecting one among a plurality of clock phases of the oversampling clock signal;
• generating an enable signal using the frame;
• performing a synchronization process on the frame using a start bit value of the frame based on the enable signal;
• and
• sampling a bit value included in the frame using the same phase as the selected one among the plurality of clock phases.