Resolving interaction between channel estimation and timing recovery

A device for signal processing, said device comprising:

• an equalizer configured to generate an equalized signal responsive to a digital input signal;
• a channel estimator coupled to said equalizer and configured to apply an estimated channel response responsive to said equalized signal to generated an estimated signal;
• a compensation logic coupled to said channel estimator and configured to:
• detect a correction in clock delay associated with said digital input signal, wherein said correction is introduced during channel estimation by said channel estimator;
• and
• adjust said estimated channel response based on said correction in clock delay to compensate said correction,
• wherein said channel estimator comprises a Finite Impulse Response (FIR) filter comprising a plurality of taps, each tap associated with a tap weight,
• and further comprising adaptation logic coupled to said channel estimator and configured to dynamically adapt tap weights of said FIR filter based on a difference between said estimated signal and said digital input signal, and wherein said correction in clock delay is related to dynamic adaptation of said estimated channel response,
• wherein said compensation logic comprises:
• a center of filter (COF) logic configured to determine a current difference between two selected tap weights of said FIR filter;
• a storage unit configured to store a nominal difference between said two selected tap weights;
• and
• an adder configured to generate an offset signal between said nominal difference and said current difference, said offset indicative of said correction in clock delay.

A receiver comprising:

• an equalizer configured to generate an equalized signal responsive to a digital input signal;
• a channel estimation filter coupled to said equalizer and configured to apply an estimated channel response responsive to said equalized signal to generate an estimated signal;
• adaptation logic coupled to said channel estimation filter and configured to dynamically adapt said estimated channel response to a current channel response of a communication channel coupled to said receiver, wherein dynamical adaptation of said estimated channel response is operable to cause a correction of clock delay associated with said digital input signal;
• and
• compensation logic coupled to said adaptation logic and configured to compensate said correction by updating said estimated channel response, wherein said compensation logic comprises;
• a center of filter (COF) logic configured to determine a current COF value based on one or more tap weights of said channel estimation filter;
• a storage unit configured to store a nominal COF;
• and
• an adder configured to generate an offset of said current COF from said nominal COF.