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US 9,882,706 B1Granted
High speed transceiver
AssigneeInphi Corporation
InventorsMarcel Louis Lugthart, Jeffrey Zachan, Linghsiao Jerry Wang, Paul Voois, Neel H. Patel, Norman L. Swenson, Scott Powell
Life of this patent
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Abstract
Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
Claims14
A transceiver comprising:
- a host-side interface configured to receive a plurality of host-side transmit data signals from a host device and to transmit a plurality of host-side receive data signals to the host device;
- a transmit path processor configured to multiplex the plurality of host-side transmit data signals to generate a line-side transmit data signal, wherein the line-side transmit data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side transmit data signals;
- wherein the line-side transmit data signal is differential, wherein the transceiver further comprises a differential transmitter configured to output the line-side transmit data signal;
- wherein the differential transmitter comprises a first digital-to-analog converter (DAC) configured to generate a first component of the line-side transmit data signal and a second DAC configured to generate a second component of the line-side transmit data signal;
- a line-side interface configured to transmit the line-side transmit data signal over an electrical cable, wherein the line-side interface is further configured to receive a line-side receive data signal from the electrical cable;
- a receive path processor configured to demultiplex the line-side receive data signal to generate the plurality of host-side receive data signals, wherein the line-side receive data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side receive data signals;
- and
- a skew adjustment circuit configured to provide skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC.
5 more elements
An active cable comprising:
- an electrical cable comprising a first pair of conductors and a second pair of conductors;
- and
- a pluggable transceiver module comprising:
- a host-side interface configured to connect to a host device, the host-side interface configured to receive a plurality of host-side transmit data signals and to transmit a plurality of host-side receive data signals;
- a transmit path processor configured to multiplex the plurality of host-side transmit data signals to generate a line-side transmit data signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side transmit data signals;
- wherein the line-side transmit data signal is differential, wherein the pluggable transceiver module further comprises a differential transmitter configured to output the line-side transmit data signal;
- a line-side interface configured to transmit the line-side transmit data signal over the first pair of conductors and to receive a line-side receive data signal from the second pair of conductors;
- wherein the differential transmitter comprises a first digital-to-analog converter (DAC) configured to generate a first component of the line-side transmit data signal and a second digital-to-analog converter (DAC) configured to generate a second component of the line-side transmit data signal, the pluggable transceiver module further comprising a skew adjustment circuit configured to provide skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC;
- and
- a receive path processor configured to demultiplex the line-side receive data signal to generate the plurality of host-side receive data signals, wherein the line-side receive data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side receive data signals.
7 more elements
A method of high speed communication in a transceiver, the method comprising:
- receiving a plurality of host-side transmit data signals from a host device;
- multiplexing the plurality of host-side transmit data signals to generate a line-side transmit data signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side transmit data signals;
- wherein the line-side transmit data signal is differential, and wherein generating the line-side transmit data signal comprises generating, by a first digital-to-analog converter (DAC) of a differential transmitter, a first component of the line-side transmit data signal, and generating, by a second digital-to-analog converter (DAC) of the differential transmitter, a second component of the line-side transmit data signal;
- transmitting the line-side transmit data signal over an electrical cable;
- receiving a line-side receive signal from the electrical cable;
- demultiplexing the line-side receive signal to generate a plurality of host-side receive data signals, the line-side receive signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side receive data signals;
- transmitting the plurality of host-side receive data signals to the host device and
- providing, by a skew adjustment circuit, a skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC.
5 more elements
Dependencies are inferred from the claim text.