Resolving meta-stability in a clock and data recovery circuit

A clock and data recovery (CDR) circuit, comprising:

• a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator;
• a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator;
• and
• a control circuit configured to determine an average phase detect result from the phase detect result signal and adjust the phase interpolator code in response to the average phase detect result being less than a threshold value.

A receiver, comprising:

• sampling circuitry configured to generate data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock;
• a phase interpolator configured to supply the sampling clock in response to a phase interpolator code;
• a phase detector configured to generate a phase detect result signal in response to the data samples and the crossing samples;
• a digital loop filter configured to filter the phase detect result signal to generate the phase interpolator code;
• and
• a control circuit configured to determine an average phase detect result from the phase detect result signal and adjust the phase interpolator code in response to the average phase detect result being less than a threshold value.