Systems and methods for partitioned root search for error locator polynomial functions in reed-solomon forward error correction decoding

A system for improving a speed of decoding digital data in a digital communication received by an electronic data receiver, the system comprising:

• a receiver that receives wired Ethernet communications that include Reed-Solomon encoded digital data;
• at least one processor of a machine;
• and
• a non-transitory machine-readable storage medium embodying instructions that, when executed by the at least one processor of the machine, cause the machine to perform operations comprising:
• specifying a partition of a plurality of elements of a Galois field into a plurality of sets;
• specifying an error locator polynomial function for a Reed-Solomon forward error correction module;
• specifying for each set of the plurality of sets, a second function dependent upon the error locator polynomial function and one or more characteristics of the respective set;
• computing the second function for each of the plurality of sets to find roots of the error locator polynomial function;
• outputting the roots of the error locator polynomial function to a Reed-Solomon forward error correction decoder module of a wired Ethernet communications system;
• and
• decoding, by the Reed-Solomon forward error correction decoder module of the wired Ethernet communications system, the digital data included in the received wired Ethernet communication using the roots.

A method of improving a speed of decoding Reed-Solomon encoded digital data, the method comprising:

• specifying, by one or more hardware processors, a partition of a plurality of elements of a Galois field into a plurality of sets;
• specifying, by one or more hardware processors, an error locator polynomial function for a Reed-Solomon forward error correction module;
• initializing, by one or more hardware processors, for each set of the plurality of sets, a second function dependent upon one or more characteristics of the respective set;
• computing, by one or more hardware processors, for each set of the plurality of sets, an update to the second function by multiplying the second function by a third function;
• determining, by one or more hardware processors, that a root has been found when a sum of the second function is null;
• outputting, by one or more hardware processors, the roots of the error locator polynomial function to a Reed-Solomon forward error correction decoder module of a wired Ethernet communications system;
• and
• decoding, by the Reed-Solomon forward error correction decoder module of the wired Ethernet communications system, the digital data included in received wired Ethernet communication using the roots.