Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof

An integrated circuit comprising:

• a plurality of logic tiles, arranged in an array of rows and columns, wherein, during operation, each logic tile includes a plurality of edges and is configurable to connect with at least one logic tile that is adjacent to and edge, and wherein each logic tile of the plurality of logic tiles includes:
• a plurality of input clock paths, wherein each input clock path is associated with an edge of the logic tile and includes circuitry configurable to receive at least one tile input clock signal from one or more logic tiles of the plurality of logic tiles;
• a plurality of output clock paths, wherein each output clock path is associated with an edge of the logic tile and includes circuitry which is configurable to transmit a tile output clock signal to one or more logic tiles of the plurality of logic tiles;
• tile clock generation circuitry, coupled to the plurality of input clock paths, which is configurable to generate at least one tile clock, having a skew, using or based on the at least one tile input clock signal wherein the skew of the at least one tile clock is balanced relative to the tile clocks generated by the tile clock generation circuitry of each logic tile of the plurality of logic tiles;
• logic circuitry, coupled to the tile clock generation circuitry, to perform operations using or based on at least one tile clock.

An integrated circuit comprising:

• a plurality of logic tiles, arranged in an array of rows and columns, wherein, during operation, each logic tile is configurable to connect with at least one logic tile that is adjacent thereto, and wherein each logic tile of the plurality of logic tiles includes:
• clock distribution and transmission circuitry, configurable to (i) receive at least one tile input clock signal from one or more logic tiles of the plurality of logic tiles which is/are adjacent thereto and (ii) to transmit at least one tile output clock signal to one or more logic tiles of the plurality of logic tiles which is/are adjacent thereto;
• tile clock generation circuitry, coupled to the clock distribution and transmission circuitry, configurable to generate at least one tile clock, having a skew, using or based on the at least one tile input clock signal wherein the skew of the at least one tile clock is balanced relative to the tile clocks generated by the tile clock generation circuitry of each logic tile of the plurality of logic tiles;
• circuitry, coupled to clock distribution and transmission circuitry, to disable circuitry of the clock distribution and transmission circuitry;
• and
• logic circuitry, coupled to the tile clock generation circuitry, to perform operations using or based on at least one tile clock.