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US 9,882,566 B1Granted
Driving circuit for non-volatile memory
AssigneeeMemory Technology Inc.
InventorsChen-Hao Po, Wu-Chang Chang
Life of this patent
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Abstract
A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives an input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.
Claims19
A driving circuit connected with a non-volatile cell array, the driving circuit comprising:
- a first transistor, wherein a source terminal and a body terminal of the first transistor are connected with a first supply voltage, a drain terminal of the first transistor is connected with a node a1, and a gate terminal of the first transistor is connected with a node b1 or a node b2;
- a second transistor, wherein a source terminal and a body terminal of the second transistor are connected with the first supply voltage, a drain terminal of the second transistor is connected with the node b1, and a gate terminal of the second transistor is connected with the node a1 or a node a2;
- a third transistor, wherein a source terminal of the third transistor is connected with a second supply voltage, a body terminal of the third transistor is connected with the first supply voltage or the node a1, and a drain terminal and a gate terminal of the third transistor are connected with the node a1;
- a fourth transistor, wherein a source terminal of the fourth transistor is connected with the second supply voltage, a body terminal of the fourth transistor is connected with the first supply voltage or the node b1, and a drain terminal and a gate terminal of the fourth transistor are connected with the node b1;
- a fifth transistor, wherein a source terminal and a body terminal of the fifth transistor are connected with the node a1, a gate terminal of the fifth transistor is connected with the second supply voltage, and a drain terminal of the fifth transistor is connected with the node a2;
- a sixth transistor, wherein a source terminal and a body terminal of the sixth transistor are connected with the node b1, a gate terminal of the sixth transistor is connected with the second supply voltage, and a drain terminal of the sixth transistor is connected with the node b2, wherein a driving signal is outputted from the node b2;
- a seventh transistor, wherein a source terminal and a body terminal of the seventh transistor are connected with the node a2, a gate terminal of the seventh transistor is connected with a third supply voltage, and a drain terminal of the seventh transistor is connected with a node a3;
- an eighth transistor, wherein a source terminal and a body terminal of the eighth transistor are connected with the node b2, a gate terminal of the eighth transistor is connected with the third supply voltage, and a drain terminal of the eighth transistor is connected with a node b3;
- a ninth transistor, wherein a drain terminal of the ninth transistor is connected with the node a3, a gate terminal of the ninth transistor is connected with a fourth supply voltage, a source terminal of the ninth transistor is connected with a node a4, and a body terminal of the ninth transistor is connected with a fifth supply voltage, wherein the fourth supply voltage is not equal to the third supply voltage;
- a tenth transistor, wherein a drain terminal of the tenth transistor is connected with the node b3, a gate terminal of the tenth transistor is connected with the fourth supply voltage, a source terminal of the tenth transistor is connected with a node b4, and a body terminal of the tenth transistor is connected with the fifth supply voltage;
- an eleventh transistor, wherein a drain terminal of the eleventh transistor is connected with the node a4, a gate terminal of the eleventh transistor receives an input signal, and a source terminal and a body terminal of the eleventh transistor are connected with the fifth supply voltage;
- a twelfth transistor, wherein a drain terminal of the twelfth transistor is connected with the node b4, a gate terminal of the twelfth transistor receives an inverted input signal, a source terminal of the twelfth transistor is connected with a sixth supply voltage, and a body terminal of the twelfth transistor is connected with the fifth supply voltage;
- a first biasing circuit connected with the node a2;
- and
- a second biasing circuit connected with the node b2.
12 more elements
A driving circuit connected with a non-volatile cell array, the driving circuit comprising:
- a first driver comprising:
- a first transistor, wherein a source terminal and a body terminal of the first transistor are connected with a first supply voltage, a drain terminal of the first transistor is connected with a node a1, and a gate terminal of the first transistor is connected with a node b1 or a node b2;
- a second transistor, wherein a source terminal and a body terminal of the second transistor are connected with the first supply voltage, a drain terminal of the second transistor is connected with the node b1, and a gate terminal of the second transistor is connected with the node a1 or a node a2;
- a third transistor, wherein a source terminal of the third transistor is connected with a second supply voltage, a body terminal of the third transistor is connected with the first supply voltage or the node a1, and a drain terminal and a gate terminal of the third transistor are connected with the node a1;
- a fourth transistor, wherein a source terminal of the fourth transistor is connected with the second supply voltage, a body terminal of the fourth transistor is connected with the first supply voltage or the node b1, and a drain terminal and a gate terminal of the fourth transistor are connected with the node b1;
- a fifth transistor, wherein a source terminal and a body terminal of the fifth transistor are connected with the node a1, a gate terminal of the fifth transistor is connected with the second supply voltage, and a drain terminal of the fifth transistor is connected with the node a2;
- a sixth transistor, wherein a source terminal and a body terminal of the sixth transistor are connected with the node b1, a gate terminal of the sixth transistor is connected with the second supply voltage, and a drain terminal of the sixth transistor is connected with the node b2;
- a seventh transistor, wherein a source terminal and a body terminal of the seventh transistor are connected with the node a2, a gate terminal of the seventh transistor is connected with a third supply voltage, and a drain terminal of the seventh transistor is connected with a node a3;
- an eighth transistor, wherein a source terminal and a body terminal of the eighth transistor are connected with the node b2, a gate terminal of the eighth transistor is connected with the third supply voltage, and a drain terminal of the eighth transistor is connected with a node b3;
- a ninth transistor, wherein a drain terminal of the ninth transistor is connected with the node a3, a gate terminal of the ninth transistor is connected with a fourth supply voltage, a source terminal of the ninth transistor is connected with a node a4, and a body terminal of the ninth transistor is connected with a fifth supply voltage, wherein the fourth supply voltage is not equal to the third supply voltage;
- a tenth transistor, wherein a drain terminal of the tenth transistor is connected with the node b3, a gate terminal of the tenth transistor is connected with the fourth supply voltage, a source terminal of the tenth transistor is connected with a node b4, and a body terminal of the tenth transistor is connected with the fifth supply voltage;
- an eleventh transistor, wherein a drain terminal of the eleventh transistor is connected with the node a4, a gate terminal of the eleventh transistor receives an input signal, and a source terminal and a body terminal of the eleventh transistor are connected with the fifth supply voltage;
- a twelfth transistor, wherein a drain terminal of the twelfth transistor is connected with the node b4, a gate terminal of the twelfth transistor receives an inverted input signal, a source terminal of the twelfth transistor is connected with a sixth supply voltage, and a body terminal of the twelfth transistor is connected with the fifth supply voltage;
- a first biasing circuit connected with the node a2;
- and
- a second biasing circuit connected with the node b2;
- a first switching circuit connected between the node b2 and a first output terminal;
- and
- a second driver connected with the first output terminal, wherein a first output signal is outputted from the first output terminal.
16 more elements
Dependencies are inferred from the claim text.