In line critical path delay measurement for accurate timing indication for a first fail mechanism

An integrated circuit, compromising:

• a first Flip Flop and a second Flip Flop;
• a plurality of multiplexers;
• a critical path delay built from plurality of combinational cells located between the first Flip Flop and a second Flip Flop, wherein a transition of an output signal of the first Flip Flop to a delay path cause a transition to an input of the second Flip Flop;
• an in-line programmable Delay Line (DLL) connected to the output and input signals of the integrated circuit critical path, wherein an oscillation loop is created in two different options—with said DLL and without said DLL using different multiplexers of the plurality of multiplexers in the circuit;
• a First Fail circuit built from a programmable Delay Line (DLL) having similar properties to the programmable Delay Line used inside the critical path configured to mimic an exact delay of the critical path in the integrated circuit;
• wherein the First Fail circuit is in a configuration that gives a pass/fail indication;
• a separate programmable voltage source connected to the First Fail circuit;
• wherein the First Fail circuit is connected to a single voltage source different from the one used by the integrated circuit and receives an identical clock as the integrated circuit is using.