US 9,882,554 B2 · Dead time control circuit for a level shifter

Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

Claims37

Dependent claims

A circuital arrangement configured to control a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the HS device and the LS device capable of withstanding a voltage higher than or equal to a first voltage, the circuital arrangement comprising:

a HS control circuit operating between a first switching voltage and a second switching voltage based on the first switching voltage, the first switching voltage being an output voltage at a common output node of the stacked HS device and LS device, the HS control circuit configured to provide a HS output control signal at a voltage higher than the first voltage to the HS device;
a LS control circuit configured to provide a LS output control signal to the LS device;
and
a dead time control circuit configured, to generate timing information for the HS output control signal and the LS output control signal,
wherein all transistor devices of the HS control circuit, the LS control circuit and the dead time controller circuit, are each configured to withstand a second voltage substantially smaller than the first voltage.

2 more elements

Dependencies are inferred from the claim text.

Dead time control circuit for a level shifter

Life of this patent

Dead time control circuit for a level shifter

Life of this patent

Abstract

Claims37