Buck-boost converters with ramp compensation

A controller used in a buck-boost converter, wherein the buck-boost converter having a first transistor coupled between an input voltage and a first switching node, a second transistor coupled between the first switching node and a reference ground, a third transistor coupled between a second switching node and the reference ground, a fourth transistor coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the controller comprises:

• a first filtering circuit configured to filter the voltage at the first switching node and generate a first ramp signal;
• a second filtering circuit configured to filter the first ramp signal and generate a first average signal;
• a third filtering circuit configured to filter the voltage at the second switching node and generate a second ramp signal;
• a fourth filtering circuit configured to filter the second ramp signal and generate a second average signal;
• a comparing circuit coupled to the first, second, third and fourth filtering circuits and configured to generate a set signal based on the first ramp signal, the first average signal, the second ramp signal, the second average signal, a reference signal, and a feedback signal indicative of the output voltage;
• a first on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the first on-time control circuit compares the on-time of the first transistor with a first time threshold and generates a first on-time control signal;
• a second on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the second on-time control circuit compares the on-time of the third transistor with a second time threshold and generates a second on-time control signal;
• a first logic circuit coupled to the comparing circuit and the first on-time control circuit, wherein based on the set signal and the first on-time control signal, the first logic circuit generates a first control signal to control the first and second transistors;
• and
• a second logic circuit coupled to the comparing circuit and the second on-time control circuit, wherein based on the set signal and the second on-time control signal, the second logic circuit generates a second control signal to control the third and fourth transistors.

A buck-boost converter comprising:

• a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured to receive an input voltage;
• a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the first transistor to form a first switching node, the second terminal is coupled to a reference ground;
• a third transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the reference ground;
• a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the third transistor to form a second switching node, the second terminal is configured to provide an output voltage;
• an inductor coupled between the first switching node and the second switching node;
• a feedback circuit configured to generate a feedback signal indicative of the output voltage;
• a first filtering circuit configured to filter the voltage at the first switching node and generate a first ramp signal;
• a second filtering circuit configured to filter the first ramp signal and generate a first average signal;
• a third filtering circuit configured to filter the voltage at the second switching node and generate a second ramp signal;
• a fourth filtering circuit configured to filter the second ramp signal and generate a second average signal;
• a comparing circuit coupled to the first to fourth filtering circuits and configured to generate a set signal based on the first ramp signal, the first average signal, the second ramp signal, the second average signal, a reference signal, and the feedback signal;
• a first on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the first on-time control circuit compares the on-time of the first transistor with a first time threshold and generates a first on-time control signal;
• a second on-time control circuit coupled to the comparing circuit, wherein based on the set signal, the second on-time control circuit compares the on-time of the third transistor with a second time threshold and generates a second on-time control signal;
• a first logic circuit coupled to the comparing circuit and the first on-time control circuit, wherein based on the set signal and the first on-time control signal, the first logic circuit generates a first control signal to control the first and second transistors;
• and
• a second logic circuit coupled to the comparing circuit and the second on-time control circuit, wherein based on the set signal and the second on-time control signal, the second logic circuit generates a second control signal to control the third and fourth transistors.